A packaged electronic device includes a package structure that encloses first and second semiconductor dies, a die attach pad with a first side attached to one of the dies, and a second side exposed along a side of the package structure, and a substrate that includes a first metal layer exposed along another side of the package structure, a second metal layer soldered to contacts of the dies, and an isolator layer that extends between and separates the first and second metal layers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A packaged electronic device, comprising: a package structure that encloses a first semiconductor die and a second semiconductor die, the package structure including a first side and an opposite second side; a die attach pad, including a first side connected to a contact of one of the first semiconductor die and the second semiconductor die, and an opposite second side exposed along the second side of the package structure; and a substrate, including: a first metal layer exposed along the first side of the package structure, a second metal layer connected to a contact of the first semiconductor die and to a contact of the second semiconductor die, and an isolator layer that extends between and separates the first and second metal layers.
2. The packaged electronic device of claim 1 , wherein the second metal layer is electrically isolated from the first metal layer.
3. The packaged electronic device of claim 2 , wherein the isolator layer includes a ceramic material.
4. The packaged electronic device of claim 2 , wherein the second side of the die attach pad is soldered to a contact of the first semiconductor die and to a contact of the second semiconductor die.
5. The packaged electronic device of claim 2 , wherein the second metal layer includes a first portion, and a second portion, and wherein the first portion is electrically isolated from the second portion.
6. The packaged electronic device of claim 1 , wherein the second metal layer includes a first portion, and a second portion, and wherein the first portion is electrically isolated from the second portion.
7. The packaged electronic device of claim 6 , wherein the first portion of the second metal layer is soldered to a contact of the first semiconductor die; wherein the first portion of the second metal layer is soldered to a contact of the second semiconductor die; and wherein the second portion of the second metal layer is soldered to a contact of the second semiconductor die.
8. The packaged electronic device of claim 7 , further comprising a lead connected to the second portion of the second metal layer, wherein lead is exposed along the second side of the package structure.
9. The packaged electronic device of claim 1 , further comprising a lead connected to the second portion of the second metal layer, wherein lead is exposed along the second side of the package structure.
10. The packaged electronic device of claim 1 , wherein the package structure includes plastic or ceramic material.
11. The packaged electronic device of claim 1 , wherein the first metal layer and the second metal layer include copper, nickel, palladium, silver or gold.
12. The packaged electronic device of claim 1 , wherein the first side of the die attach pad is solder connected to the contact of one of the first semiconductor die.
13. The packaged electronic device of claim 1 , wherein the second metal layer is solder connected to a contact of the first semiconductor die and to a contact of the second semiconductor die.
14. The package electronic device of claim 1 , wherein the isolator layer 112 has a thickness of 100 μm or more and about 300 μm or less.
15. The package electronic device of claim 14 , wherein the first metal layer has a thickness of 50 μm or more and 100 μm or less, and the second metal layer has a thickness of 50 μm or more and 100 μm or less.
16. A packaged electronic device, comprising: a die attach pad, including a first side, and an opposite second side; a first semiconductor die, including a first side connected to the first side of the die attach pad, and an opposite second side, the second side of the first semiconductor die including a first contact and a second contact; a second semiconductor die, including a first side connected to the first side of the die attach pad, and an opposite second side, the second side of the second semiconductor die including a first contact and a second contact; a substrate, including: an isolatorg layer, including a first side and an opposite second side, a first metal layer formed on the first side of the isolatorg layer, and a second metal layer formed on the second side of the isolatorg layer, the second metal layer connected to the second side of the first semiconductor die, the second metal layer connected to the second side of the second semiconductor die, and the second metal layer electrically isolated from the first metal layer; and a package structure that encloses the first semiconductor die, the second semiconductor die, a portion of the die attach pad, and a portion of the substrate, the package structure including: a first side that exposes a portion of the first metal layer of the substrate, and a second side that exposes a portion of the second side of the die attach pad.
17. The packaged electronic device of claim 16 , wherein the second metal layer includes a first portion and a second portion, and wherein the first portion is electrically isolated from the second portion.
18. The packaged electronic device of claim 17 , wherein the first portion of the second metal layer electrically connects a contact of the second side of the first semiconductor die to a first contact of the second side of the second semiconductor die; and wherein the second portion of the second metal layer is connected to a second contact of the second semiconductor die.
19. The packaged electronic device of claim 18 , further comprising a lead connected to the second portion of the second metal layer; wherein the second side of the package structure exposes a portion of the lead.
20. The packaged electronic device of claim 17 , further comprising a lead connected to the second portion of the second metal layer; wherein the second side of the package structure exposes a portion of the lead.
21. The packaged electronic device of claim 17 , wherein the first metal layer and the second metal layer include copper, nickel, palladium, silver or gold.
22. The packaged electronic device of claim 16 , wherein the first metal layer and the second metal layer include copper, nickel, palladium, silver or gold.
23. The packaged electronic device of claim 16 , wherein the isolator layer is an electrical insulator.
24. The packaged electronic device of claim 16 , wherein the isolator layer includes ceramic material.
25. The packaged electronic device of claim 16 , wherein the package structure includes plastic or ceramic material.
26. The package electronic device of claim 16 , wherein the isolator layer 112 has a thickness of 100 μm or more and about 300 μm or less.
27. The package electronic device of claim 16 , wherein the first metal layer has a thickness of 50 μm or more and 100 μm or less, and the second metal layer has a thickness of 50 μm or more and 100 μm or less.
28. A method, comprising: attaching a first side of a first semiconductor die to a first side of a die attach pad; attaching a first side of a second semiconductor die to the first side of the die attach pad; attaching a second metal layer of a second side of a substrate to a second side of the first semiconductor die and to a second side of the second semiconductor die; and forming a package structure that encloses the first semiconductor die and a second semiconductor die, the package structure including a first side that exposes a first metal layer of a first side of the substrate, and a second side that exposes a second side of the die attach pad.
29. The method of claim 28 , further comprising: attaching the second metal layer of the second side of the substrate to a lead.
30. The method of claim 29 , wherein attaching the second metal layer of the second side of the substrate to the lead includes: attaching a conductive post to the lead; and attaching the second metal layer of the second side of the substrate to the conductive post; and wherein the second side of the package structure exposes a portion of the lead.
31. The method of claim 28 , wherein attaching the second metal layer of the second side of the substrate to the second side of the first semiconductor die and to the second side of the second semiconductor die includes: soldering the second metal layer of the second side of the substrate to a contact of the second side of the first semiconductor die, soldering the second metal layer of the second side of the substrate to a contact of the second side of the second semiconductor die.
32. An apparatus, comprising: a first side of a first semiconductor die connected to a first side of a die attach pad; a first side of a second semiconductor die connected to the first side of the die attach pad; a second metal layer of a second side of a substrate connected to a second side of the first semiconductor die and to a second side of the second semiconductor die; and a package structure covering the first semiconductor die and a second semiconductor die, the package structure including a first side that exposes a first metal layer of a first side of the substrate, and a second side that exposes a second side of the die attach pad.
33. The apparatus of claim 32 , further comprising: the second metal layer of the second side of the substrate connected to a lead.
34. The apparatus of claim 33 , wherein the connection of the second metal layer of the second side of the substrate to the lead includes: a conductive post connected to the lead; and the second metal layer of the second side of the substrate connected to the conductive post; and wherein the second side of the package structure exposes a portion of the lead.
35. The apparatus of claim 32 , wherein the connection of the second metal layer of the second side of the substrate to the second side of the first semiconductor die and to the second side of the second semiconductor die includes: the second metal layer of the second side of the substrate soldered to a contact of the second side of the first semiconductor die, the second metal layer of the second side of the substrate soldered to a contact of the second side of the second semiconductor die.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 9, 2019
December 29, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.