The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: an array of memory cells, including a plurality of bit lines; a plurality of bit line circuits, a bit line circuit in the plurality of bit line circuits including an input node in current flow communication with a corresponding bit line in the plurality of bit lines, a first transistor between the input node and an intermediate node, a second transistor between the intermediate node and a sensing node, a third transistor between the sensing node and a supply terminal, and an output circuit to generate a data signal based on a voltage on the sensing node; and control circuits coupled to the plurality of bit line circuits to control a sensing sequence, including circuits: during a first phase to apply a bit line clamp voltage to the first transistor, a transfer voltage to the second transistor and a third voltage to the third transistor to charge the sensing node to a pre-charge voltage; during a second phase to adjust the third voltage applied to the third transistor to a keeping level voltage, wherein the keeping level causes the third transistor to clamp the sensing node from falling below a discharge voltage level having a fixed voltage difference from the keeping level voltage.
2. The device of claim 1 , wherein the sensing sequence includes generating the data signal based on a voltage on the sensing node after the second phase.
3. The device of claim 1 , wherein a source/drain terminal of the first transistor is connected directly to a first source/drain terminal of the second transistor, and a second source/drain terminal of the second transistor is connected directly to the sensing node, the intermediate node having a voltage level based on the transfer voltage applied to the second transistor.
4. The device of claim 3 , wherein a source/drain terminal of the third transistor is connected directly to the sensing node.
5. The device of claim 1 , wherein the fixed voltage difference is a gate-to-source voltage V GS of the third transistor.
6. The device of claim 1 , wherein the discharge level is above the transfer voltage during the second phase by at least a gate-to-source voltage of the second transistor.
7. The device of claim 1 , wherein the voltage on the intermediate node is maintained during the second phase at a voltage based on the transfer voltage applied to a gate of the second transistor.
8. The device of claim 1 , including a capacitor having one terminal at the sensing node, and the sensing sequence boosts the sensing node to a boosted voltage during the second phase by applying a pulse to a second terminal of the capacitor.
9. The device of claim 7 , the bit line circuit including an output circuit having a transistor with a gate connected to the sensing node, and a source/drain terminal connected to the second terminal of the capacitor.
10. A method for operating a memory device comprising an array of memory cells, including a plurality of bit lines, a plurality of bit line circuits, a bit line circuit in the plurality of bit line circuits including an input node in current flow communication with a corresponding bit line in the plurality of bit lines, a bit line clamp transistor connected between the input node and an intermediate node, a transfer transistor connected between the intermediate node and a sensing node, a current source transistor connected between the sensing node and a supply terminal, and an output circuit to generate a data signal based on a voltage on the sensing node, the method comprising: during a first phase applying a bit line clamp voltage to the first transistor, a transfer voltage to the second transistor and a third voltage to the third transistor to charge the sensing node to a pre-charge voltage; during a second phase adjusting the third voltage applied to the third transistor to a keeping level voltage, wherein the keeping level voltage causes the third transistor to clamp the sensing node from falling below a discharge voltage level having a fixed voltage difference from the keeping level voltage.
11. The method of claim 10 , including generating the data signal based on a voltage on the sensing node after the second phase.
12. The method of claim 10 , wherein a source/drain terminal of the bit line clamp transistor is connected directly to a first source/drain terminal of the transfer transistor, and a second source/drain terminal of the transfer transistor is connected directly to the sensing node, the intermediate node having a voltage level based on the transfer voltage applied to the transfer transistor.
13. The method of claim 12 , wherein a source/drain terminal of the current source transistor is connected directly to the sensing node.
14. The method of claim 10 , wherein the discharge level is below the keeping level voltage by a gate-to-source voltage of the third transistor.
15. The method of claim 10 , wherein the discharge level is above the transfer voltage during the second phase by at least a gate-to-source voltage of transfer transistor.
16. The method of claim 10 , wherein the voltage on the intermediate node is maintained during the second phase at a voltage based on the transfer voltage applied to a gate of transfer transistor.
17. The method of claim 10 , wherein the device includes a capacitor having one terminal at the sensing node, and including boosting the sensing node to the boosted voltage during the second phase by applying a pulse to a second terminal of the capacitor.
18. The memory of claim 1 , wherein the array includes a plurality of word lines, and the control circuits includes circuits to apply a word line voltage to a selected word line to access a selected memory cell during the second phase, to discharge the sensing node when the selected memory cell has a threshold below the word line voltage.
19. The method of claim 10 , wherein the array includes a plurality of word lines, and including applying a word line voltage to a selected word line to access a selected memory cell during the second phase, to discharge the sensing node when the selected memory cell has a threshold below the word line voltage.
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February 15, 2019
January 5, 2021
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