Bias circuit and amplification apparatus

1. An amplification apparatus comprising: a bias circuit for supplying a bias voltage; and an amplification circuit to which the bias voltage is configured to be supplied from the bias circuit, the bias circuit comprising: a first voltage outputting unit comprising: a first current source configured to increase and decrease a first output current depending on the bias voltage; and a first voltage dropping portion including a first transistor which is a MOSFET with a first polarity and through which the first output current from the first current source flows as a drain current, the first voltage outputting unit being configured to output a first output voltage from a connection point between the first current source and the first voltage dropping portion; a second voltage outputting unit comprising: a second current source configured to output a constant current as a second output current; and a second voltage dropping portion including a second transistor which is a MOSFET with a second polarity different from the first polarity and through which the second output current from the second current source flows as a drain current, the second voltage outputting unit being configured to output a second output voltage from a connection point between the second current source and the second voltage dropping portion; and a voltage comparator configured to output the bias voltage, and increase and decrease the bias voltage such that the first and second output voltages become equal, based on a difference between the first and second output voltages, the amplification circuit comprising: a source follower stage comprising: a third current source configured to increase and decrease a third output current depending on the bias voltage; and a third transistor which is a MOSFET with the first polarity and has a gate to which an input signal is configured to be inputted, the third output current from the third current source being configured to flow as a drain current through the third transistor; and an amplification stage comprising a fourth transistor which is a MOSFET with the second polarity and has a gate to which an output of the source follower stage is configured to be inputted, the amplification stage being configured to amplify the output of the source follower stage.

2. The amplification apparatus according to claim 1 , wherein the first transistor is diode-connected, and is connected to an output terminal of the first current source; and the second transistor is diode-connected, and is connected to an output terminal of the second current source.

3. The amplification apparatus according to claim 1 , further comprising a gate voltage applying unit configured to apply, as a gate voltage of the first transistor, a center voltage of an amplitude of the input signal to the amplification circuit.

4. The amplification apparatus according to claim 2 , wherein the first voltage dropping portion comprises a plurality of first transistors connected in series, each of the plurality of first transistors being defined as the first transistor.

5. The amplification apparatus according to claim 2 , wherein the second voltage dropping portion comprises a plurality of second transistors connected in series, each of the plurality of second transistors being defined as the second transistor.

6. The amplification apparatus according to claim 2 , wherein the first voltage dropping portion further comprises a first resistance element connected in series to the first transistor.

7. The amplification apparatus according to claim 2 , wherein the second voltage dropping portion further comprises a second resistance element connected in series to the second transistor.

8. The amplification apparatus according to claim 1 , wherein each of the first, second, third and fourth transistors has a structure comprising: a semiconductor pillar having a semiconductor region as a channel on a central part, a drain region on one end, and a source region on the other end; a gate electrode provided around the central part of the semiconductor pillar; and a gate oxide film provided between the gate electrode and the semiconductor pillar.

9. The amplification apparatus according to claim 1 , wherein the first current source is a fifth transistor that is a MOSFET to which the bias voltage is configured to be applied as a gate voltage, and the third current source is a sixth transistor that is a MOSFET to which the bias voltage is configured to be applied as a gate voltage.

10. The amplification apparatus according to claim 1 , wherein the first current source is a fifth transistor, the third current source is a sixth transistor, and a proportion between a ratio of a gate width to a gate length of the fifth transistor and a ratio of a gate width to a gate length of the sixth transistor is equal to a proportion between a ratio of a gate width to a gate length of the first transistor and a ratio of a gate width to a gate length of the third transistor.

11. The amplification apparatus according to claim 1 , wherein the first current source includes fifth transistors connected in series, and the third current source includes sixth transistors connected in series.

12. The amplification apparatus according to claim 1 , wherein the amplification circuit comprises: a first source follower stage to which a first input signal is configured to be inputted, the first source follower stage being defined as the source follower stage, the first input signal being defined as the input signal; and a second source follower stage to which a second input signal is configured to be inputted, the second source follower stage being defined as an additional source follower stage, the second input signal being defined as an additional input signal, wherein the amplification stage comprises: a pair of fourth transistors configured to perform differential amplification, the pair of fourth transistors being defined as the fourth transistor and an additional fourth transistor; and a tail current transistor that is a MOSFET as a tail current source and has a drain connected to sources of the pair of fourth transistors, and a source of the second transistor is connected to the sources of the pair of fourth transistors.

13. A bias circuit for supplying a bias voltage to an amplification circuit, the amplification circuit including a first amplification transistor being a MOSFET with a first polarity and a second amplification transistor being a MOSFET with a second polarity different from the first polarity, the bias circuit comprising: a first voltage outputting unit comprising: a first current source configured to increase and decrease a first output current depending on the bias voltage; and a first voltage dropping portion including a first transistor which is a MOSFET with the first polarity and through which the first output current from the first current source flows as a drain current, the first voltage outputting unit being configured to output a first output voltage from a connection point between the first current source and the first voltage dropping portion; a second voltage outputting unit comprising: a second current source configured to output a constant current as a second output current; and a second voltage dropping portion including a second transistor which is a MOSFET with the second polarity and through which the second output current from the second current source flows as a drain current, the second voltage outputting unit being configured to output a second output voltage from a connection point between the second current source and the second voltage dropping portion; and a voltage comparator configured to output the bias voltage to the amplification circuit and the first current source, and increase and decrease the bias voltage such that the first and second output voltages become equal, based on a difference between the first and second output voltages.