Integrated circuit and detection method for multi-chip status thereof

1. An integrated circuit, comprising: at least one chip, having a stack status pin and a busy pin, wherein the at least one chip applies a bias voltage on the busy pin according to a voltage status of the stack status pin, and the at least one chip detects an indication voltage on the busy pin, and determines whether a number of the at least chip is plural according to the indication voltage on the busy pin.

2. The integrated circuit as claimed in claim 1 , wherein the at least one chip compares the indication voltage with a reference voltage to determine whether the number of the at least one chip is plural, when the indication voltage is greater than the reference voltage, the number of the at least one chip is plural, and when the indication voltage is smaller than the reference voltage, the number of the at least one chip is one.

3. The integrated circuit as claimed in claim 1 , wherein the at least one chip applies the bias voltage on the busy pin according to the voltage status of the stack status pin during an initial status setting time section.

4. The integrated circuit as claimed in claim 1 , wherein the at least one chip comprises: a first chip, having a first stack status pin and a first busy pin, and applying a first bias voltage on the first busy pin according to a voltage status of the first stack status pin; and a second chip, having a second stack status pin and a second busy pin, and applying a second bias voltage on the second busy pin according to a voltage status of the second stack status pin, wherein the first busy pin and the second busy pin are coupled to each other.

5. The integrated circuit as claimed in claim 4 , wherein the first stack status pin is in a floating status, and the first chip applies the first bias voltage on the first busy pin, wherein the second stack status pin has a plurality of sub-pins, at least one of the sub-pins is in a non-floating status, and the second chip applies the second bias voltage on the second busy pin, and voltages values of the first bias voltage and the second bias voltage are different.

6. The integrated circuit as claimed in claim 4 , wherein driving capability of the first bias voltage is different to driving capability of the second bias voltage.

7. The integrated circuit as claimed in claim 1 , wherein the at least one chip obtains a stack position of the at least one chip according to the voltage status of the stack status pin.

8. The integrated circuit as claimed in claim 1 , wherein the at least one chip comprises: a bias generation circuit, coupled to the stack status pin and the busy pin, and applying the bias voltage on the busy pin according to the voltage status of the stack status pin.

9. The integrated circuit as claimed in claim 1 , wherein the at least one chip comprises: a detection circuit, coupled to the busy pin, and determining whether the number of the at least one chip is plural according to the indication voltage.

10. A detection method for multi-chip status, comprising: configuring a stack status pin and a busy pin in at least one chip, and applying a bias voltage on the busy pin according to a voltage status of the stack status pin; and detecting an indication voltage on the busy pin by the at least one chip, and determining whether a number of the at least chip is plural according to the indication voltage on the busy pin.

11. The detection method for multi-chip status as claimed in claim 10 , wherein the at least one chip compares the indication voltage with a reference voltage to determine whether the number of the at least one chip is plural, wherein when the indication voltage is greater than the reference voltage, the number of the at least one chip is plural, and when the indication voltage is smaller than the reference voltage, the number of the at least one chip is one.

12. The detection method for multi-chip status as claimed in claim 10 , wherein the step of applying the bias voltage on the busy pin according to the voltage status of the stack status pin comprises: applying the bias voltage on the busy pin according to the voltage status of the stack status pin during an initial status setting time section.

13. The detection method for multi-chip status as claimed in claim 10 , wherein the at least one chip comprises a first chip and at least one second chip, and the step of applying the bias voltage on the busy pin according to the voltage status of the stack status pin comprises: applying a first bias voltage on a first busy pin by the first chip according to a voltage status of a first stack status pin; and applying a second bias voltage on a second busy pin by the at least one second chip according to a voltage status of a second stack status pin, wherein the first busy pin and the second busy pin are coupled to each other.

14. The detection method for multi-chip status as claimed in claim 13 , wherein the step of applying the first bias voltage on the first busy pin by the first chip according to the voltage status of the first stack status pin comprises: the first stack status pin being in a floating status, and applying the first bias voltage on the first busy pin by the first chip; and the step of applying the second bias voltage on the second busy pin by the at least one second chip according to the voltage status of the second stack status pin comprises: at least one of sub-pins of the at least one second chip being in a non-floating status, and applying the second bias voltage on the second busy pin by the at least one second chip, wherein voltages values of the first bias voltage and the second bias voltage are different.

15. The detection method for multi-chip status as claimed in claim 13 , wherein driving capability of the first bias voltage is different to driving capability of the second bias voltage.