Location dependent impedance mitigation in non-volatile memory

1. An apparatus comprising: NAND strings comprising non-volatile memory cells; a first set of pathways connected to the NAND strings, the first set of pathways having first impedances that depend on location of respective NAND strings; a second set of pathways connected to the NAND strings, the second set of pathways having second impedances; and one or more control circuits configured to compensate for location dependent impedance mismatches between respective pairs of the pathways during memory operations on the non-volatile memory cells, wherein each pair of the pathways comprises a first member of the first set of pathways and a second member of the second set of pathways connected to the same NAND string, wherein the compensating comprises controlling start times of first signals applied to the first set of pathways and second signals applied to the second set of pathways based on locations of selected NAND strings in order to compensate for the location dependent impedance mismatches between the respective pairs of the pathways.

2. The apparatus of claim 1 , wherein the compensating further comprises: controlling steady state magnitudes of the first signals applied to the first set of pathways and the second signals applied to the second set of pathways based on the locations of the selected NAND strings in order to compensate for the location dependent impedance mismatches between the respective pairs of the pathways.

3. The apparatus of claim 1 , wherein the compensating further comprises: controlling ramp times of the first signals applied to the first set of pathways and the second signals applied to the second set of pathways based on the location of selected NAND strings in order to compensate for the location dependent impedance mismatches between the respective pairs of the pathways.

4. The apparatus of claim 1 , wherein: the first set of pathways reside along a bit line connected to NAND strings of the non-volatile memory cells in different blocks of the non-volatile memory cells, the first impedances depend on location of the different blocks; and the second set of pathways reside along a global drain side select line that connects to the NAND strings in the different blocks, the second impedances depend on location of the different blocks.

5. The apparatus of claim 1 , wherein: the first set of pathways reside along a global source side select line that connects to NAND strings in different blocks of the non-volatile memory cells, the first impedances depend on location of the different blocks; and the second set of pathways reside along a source line connected to the NAND strings in the different blocks, the second impedances depend on location of the different blocks.

6. The apparatus of claim 1 , wherein: the first set of pathways reside along a bit line connected to NAND strings in different blocks of the non-volatile memory cells; and the second set of pathways reside along a source line connected to the NAND strings in the different blocks.

7. The apparatus of claim 1 , further comprising: a third set of pathways connected to the NAND strings; and a fourth set of pathways connected to the NAND strings, wherein the one or more control circuits are configured to control first voltages applied to the third set of pathways and second voltages applied to the fourth set of pathways based on location of selected NAND strings in order to compensate for the location dependent impedance mismatch between the respective pairs of the pathways.

8. The apparatus of claim 7 , wherein: the first set of pathways are connected to first terminals of first select transistors on NAND strings in different blocks of the non-volatile memory cells; the second set of pathways are connected to first terminals of second select transistors on the NAND strings in the different blocks; the third set of pathways are connected to second terminals of the first select transistors; and the fourth set of pathways are connected to second terminals of the second select transistors.

9. A method comprising: determining a relationship between a first signal and a second signal to compensate for an impedance mismatch between a first pathway to a selected block comprising non-volatile memory cells and a second pathway to the selected block, wherein the relationship depends on location of the selected block; applying the first signal from a first driver connected through the first pathway to the selected block; and applying the second signal from a second driver connected through the second pathway to the selected block, wherein the relationship between the first signal and the second signal comprises a delay of the second signal relative to the first signal, wherein the delay depends on the location of the selected block.

10. The method of claim 9 , wherein the relationship between the first signal and the second signal further comprises: a first steady state magnitude of the first signal relative to a second steady state magnitude of the second signal, wherein the relationship of the first and the second steady state magnitudes depends on the location of the selected block.

11. The method of claim 9 , wherein: the first pathway resides along a bit line connected to a first select transistor in the selected block; and the second pathway comprises a source line connected to a second select transistor in the selected block.

12. The method of claim 11 , wherein applying the first signal from the first driver and applying the second signal from the second driver comprises: generating a first gate induced drain leakage (GIDL) current in the first select transistor; and generating a second gate induced drain leakage (GIDL) current in the second select transistor.

13. A non-volatile storage device, comprising: a plurality of blocks comprising NAND strings of non-volatile memory cells and select transistors; a first driver configured to provide a first voltage for a memory operation; a first set of pathways configured to deliver the first voltage to a first set of the select transistors in different blocks of the plurality of blocks; a second driver configured to provide a second voltage for the memory operation; a second set of pathways configured to deliver the second voltage to either the first set of the select transistors or a second set of the select transistors in the different blocks; and one or more control circuits configured to compensate for resistance-capacitance differences between pairs of pathways, each pair comprising a pathway in the first set of pathways and a corresponding pathway in the second set of pathways that end in the same respective block, wherein the resistance-capacitance differences depend on first distances between the first driver to the respective blocks and second distances between the second driver to the respective blocks, wherein the compensating comprises controlling delays between first signals applied to the first set of pathways and second signals applied to the second set of pathways based on the first distances and the second distances in order to compensate for the resistance-capacitance differences.

14. The non-volatile storage device of claim 13 , wherein the compensating further comprises: controlling steady state magnitudes of the first signals applied to the first set of pathways and the second signals applied to the second set of pathways based on the first and the second distances in order to compensate for the resistance-capacitance differences.

15. The non-volatile storage device of claim 13 , wherein: the first set of pathways reside along a bit line connected to the first set of the select transistors; and the second set of pathways reside along a global drain side select line connected to the first set of the select transistors.

16. The non-volatile storage device of claim 13 , wherein: the first set of pathways reside along a source line connected to the first set of the select transistors; and the second set of pathways reside along a global source side select line connected to the first set of the select transistors.

17. The non-volatile storage device of claim 13 , wherein: the first set of pathways reside along a bit line connected to the first set of the select transistors; and the second set of pathways reside along a source line connected to the second set of the select transistors.