A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: bonding a first package to a second package to form a third package, wherein the first package is an Integrated Fan-Out (InFO) package comprising: a first plurality of package components, wherein the first plurality of package components comprise device dies; and a first encapsulating material encapsulating the first plurality of package components therein; placing at least a portion of the third package into a first recess in a Printed Circuit Board (PCB), wherein at a time of the placing, the first package is an unsawed reconstructed wafer, and wherein the first recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB; and performing wire bonding to electrically connect the third package to the PCB.
2. The method of claim 1 , further comprising forming the second package comprising: forming a plurality of redistribution lines over a substrate, wherein the plurality of redistribution lines is between the substrate and the first package.
3. The method of claim 1 , further comprising forming the second package comprising: encapsulating a second plurality of package components in a second encapsulating material; and forming a plurality of redistribution lines over and electrically connecting to the second plurality of package components, wherein the second plurality of package components comprise additional device dies.
4. The method of claim 3 , wherein the second package is an un-sawed wafer.
5. The method of claim 1 , further comprising forming the first package comprises: encapsulating the first plurality of package components in the first encapsulating material; and trimming edge portions of the first encapsulating material.
6. The method of claim 1 , wherein the PCB further comprises a second recess extending from the bottom surface of the PCB to the intermediate level, and the method further comprises: attaching a cooling system to the third package, wherein the cooling system extends into the second recess, and wherein the PCB is free from solder regions directly underlying the cooling system.
7. The method of claim 1 , further comprising adhering a metal plate to the PCB through a Thermal Interface Material (TIM), wherein the PCB comprises a dummy metal feature penetrating through the PCB, with the TIM overlapping the dummy metal feature.
8. A method comprising: reconstructing a first wafer comprising: encapsulating a first plurality of package components in a first encapsulating material, wherein the first plurality of package components comprise different types of device dies; forming a first plurality of Redistribution Lines (RDLs) overlapping the first encapsulating material and the first plurality of package components; and forming first electrical connectors over and electrically connecting to the first plurality of RDLs; reconstructing a second wafer; trimming edge portions of the first wafer, wherein after the trimming, all active devices and RDLs are left in the first wafer; after the trimming, bonding the first wafer to the second wafer to form a package; adhering the package to a printed circuit board; and electrically connecting first conductive features on the package to second conductive features on the printed circuit board.
9. The method of claim 8 , wherein the reconstructing the second wafer comprises: encapsulating a second plurality of package components in a second encapsulating material; and forming a second plurality of RDLs connecting to the second plurality of package components.
10. The method of claim 9 , wherein after the trimming, all device dies encapsulated by the first encapsulating material remain in the first wafer that has been bonded to the second wafer, and the all device dies are in the package when attached to the printed circuit board.
11. The method of claim 8 , wherein the reconstructing the second wafer comprises: forming a second plurality of RDLs over a substrate, wherein the second plurality of RDLs are between the substrate and the first wafer.
12. The method of claim 8 , wherein the reconstructing the second wafer comprises: encapsulating a second plurality of package components in a second encapsulating material; and forming a second plurality of RDLs over and electrically connecting to the second plurality of package components.
13. The method of claim 8 , further comprises dispensing an underfill between the first wafer and the second wafer.
14. The method of claim 8 , further comprising attaching a cooling system from a bottom side of the package, wherein a portion of the cooling system extends into the printed circuit board, and wherein a portion of the cooling system extends below a bottom surface of the printed circuit board.
15. A method comprising: forming a first reconstructed wafer, wherein the first reconstructed wafer comprises: a first plurality of device dies; and a first encapsulant encapsulating the first plurality of device dies therein; forming a second reconstructed wafer, wherein the second reconstructed wafer comprises: a second plurality of device dies; and a second encapsulant encapsulating the second plurality of device dies therein; bonding the first reconstructed wafer to the second reconstructed wafer; and after the bonding, placing the second reconstructed wafer into a recess in a package component, wherein at a time of the placing, both of the first reconstructed wafer and the second reconstructed wafer are unsawed round wafers, and wherein the package component comprises redistribution lines therein, and wherein the first reconstructed wafer is higher than the package component.
16. The method of claim 15 , wherein the package component comprises: a first conductive feature penetrating through the package component, wherein the first conductive feature is on a first side of the second reconstructed wafer, wherein the first conductive feature is electrically connected to a metal pad in the package component; and a second conductive feature penetrating through the package component, wherein the second conductive feature is directly under the second reconstructed wafer.
17. The method of claim 15 further comprising forming wire bonds to electrically connect the second reconstructed wafer to the package component.
18. The method of claim 15 further comprising adhering a metal plate to the package component through a first Thermal Interface Material (TIM), with the metal plate being placed in the recess, wherein the second reconstructed wafer is placed over the metal plate.
19. The method of claim 18 , wherein the second reconstructed wafer is adhered to the metal plate through a second TIM.
20. The method of claim 15 , wherein the first plurality of device dies comprises different types of device dies.
21. The method of claim 16 , wherein the first conductive feature comprises: a first conductive pad and a second conductive pad; and a conductive trace connecting the first conductive pad and the second conductive pad.
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October 15, 2018
February 9, 2021
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