Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An image sensor comprising an array of imaging pixels, wherein an imaging pixel of the array of imaging pixels comprises: a photodiode; a floating diffusion region; a charge storage region; first and second transistors interposed between the photodiode and the charge storage region; a power supply terminal; third and fourth transistors interposed between the photodiode and the power supply terminal; and fifth and sixth transistors interposed between the charge storage region and the floating diffusion region.
2. The image sensor defined in claim 1 , wherein the first transistor has a gate that receives a horizontal transfer control signal and wherein the second transistor has a gate that receives a vertical transfer control signal.
3. The image sensor defined in claim 2 , wherein charge is transferred from the photodiode to the charge storage region only when both the first and second transistors are asserted.
4. The image sensor defined in claim 2 , wherein the image sensor has a first column of imaging pixels and a first row of imaging pixels, wherein the second transistor of each imaging pixel in the first column receives the same vertical transfer control signal, and wherein the first transistor of each imaging pixel in the first row receives the same horizontal transfer control signal.
5. The image sensor defined in claim 2 , wherein the third transistor has a gate that receives an additional horizontal transfer control signal and the fourth transistor has a gate that receives an additional vertical transfer control signal.
6. The image sensor defined in claim 1 , wherein the photodiode is coupled to the power supply terminal when the third and fourth transistors are asserted.
7. The image sensor defined in claim 1 , wherein the first transistor has a gate that receives a first horizontal transfer control signal, wherein the second transistor has a gate that receives a first vertical transfer control signal, wherein the third transistor has a gate that receives a second horizontal transfer control signal, wherein the fourth transistor has a gate that receives a second vertical transfer control signal, wherein the fifth transistor has a gate that receives a third horizontal transfer control signal, and wherein the sixth transistor has a gate that receives a third vertical transfer control signal.
8. An image sensor comprising an array of imaging pixels, wherein an imaging pixel of the array of imaging pixels comprises: a photodiode; a bias voltage supply terminal; a first anti-blooming transistor having a first terminal coupled to the photodiode, a second terminal, and a gate that receives a horizontal control signal; a second anti-blooming transistor having a first terminal coupled to the second terminal of the first anti-blooming transistor, a second terminal coupled to the bias voltage supply terminal, and a gate that receives a vertical control signal; a charge storage region; first and second transfer transistors that are interposed between the photodiode and the charge storage region; a floating diffusion region; and third and fourth transfer transistors that are interposed between the charge storage region and the floating diffusion region.
9. The image sensor defined in claim 8 , wherein the photodiode is coupled to the bias voltage supply terminal when the first and second anti-blooming transistors are asserted.
10. The image sensor defined in claim 8 , wherein the image sensor has a first column of imaging pixels and a first row of imaging pixels, wherein the first anti-blooming transistor of each imaging pixel in the first row receives the same horizontal transfer control signal, and wherein the second anti-blooming transistor of each imaging pixel in the first column receives the same vertical transfer control signal.
11. The image sensor defined in claim 8 , wherein the first transfer transistor receives a second horizontal control signal, wherein the second transfer transistor receives a second vertical control signal, wherein the third transfer transistor receives a third horizontal control signal and wherein the fourth transfer transistor receives a third vertical control signal.
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October 10, 2019
February 9, 2021
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