An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a substrate; a first dielectric layer over the substrate; and a first conductive line, a second conductive line, and a third conductive line that are disposed in the first dielectric layer and laterally adjacent to each other, the first conductive line being between the second conductive line and the third conductive line, the first conductive line having air gaps on opposing sides, the air gaps extending into the first dielectric layer from an uppermost surface of the first dielectric layer distal from the substrate, the air gaps exposing opposing sidewalls of the first conductive line, bottoms of the air gaps being further from the substrate than a bottom surface of the first conductive line facing the substrate.
2. The semiconductor device of claim 1 , further comprising: fourth conductive lines in the first dielectric layer, the fourth conductive lines having a width larger than a width of the first conductive line, wherein no air gap is disposed between the fourth conductive lines; a second dielectric layer over the first dielectric layer; and a via extending through the second dielectric layer and contacting one of the fourth conductive lines, the first conductive line being covered by the second dielectric layer.
3. The semiconductor device of claim 2 , wherein no via contacts the first conductive line.
4. The semiconductor device of claim 1 , wherein each of the air gaps has an upper portion proximate to the uppermost surface of the first dielectric layer and has a lower portion underlying the upper portion, wherein the upper portion has a first width that is smaller than a second width of the lower portion.
5. The semiconductor device of claim 4 , wherein the upper portion has straight sidewalls and the lower portion has curved sidewalls.
6. The semiconductor device of claim 4 , wherein upper sidewalls of the first conductive line are exposed by the air gaps, and lower sidewalls of the first conductive line are covered by the first dielectric layer.
7. The semiconductor device of claim 1 , wherein a first air gap of the air gaps exposes a first sidewall of the first dielectric layer, and a second air gap of the air gaps exposes a second sidewall of the first dielectric layer, wherein a distance between the first sidewall and the second sidewall of the first dielectric layer decreases as the air gaps extend into the first dielectric layer toward the substrate.
8. The semiconductor device of claim 1 , wherein a sidewall of the second conductive line facing the first conductive line is covered by a first portion of the first dielectric layer, and a sidewall of the third conductive line facing the first conductive line is covered by a second portion of the first dielectric layer.
9. A semiconductor device comprising: a substrate; a first dielectric layer over the substrate; a plurality of conductive lines in the first dielectric layer; a first void adjacent to a first conductive line of the plurality of conductive lines, the first void extending from an upper surface of the first dielectric layer distal from the substrate into the first dielectric layer by a first depth, the first void exposing a first sidewall of the first conductive line; and a second void adjacent to the first conductive line, the second void extending from the upper surface of the first dielectric layer into the first dielectric layer by a second depth, the first void and the second void being on opposing sides of the first conductive line, the second void exposing a second sidewall of the first conductive line, the first depth and the second depth being smaller than a third depth of the first conductive line measured along a direction perpendicular to the upper surface of the first dielectric layer.
10. The semiconductor device of claim 9 , wherein the first void further exposes a first sidewall of the first dielectric layer, wherein an upper portion of the first sidewall of the first dielectric layer has a linear profile, and a lower portion of the first sidewall of the first dielectric layer has a curved profile.
11. The semiconductor device of claim 9 , wherein upper portions of the first and second sidewalls of the first conductive line are exposed by the first and second voids, and lower portions of the first and second sidewalls of the first conductive line are covered by the first dielectric layer.
12. The semiconductor device of claim 9 , wherein a second conductive line of the plurality of conductive lines is laterally adjacent to the first conductive line, wherein a width of the second conductive line is between 1.03 and 3 times larger than a width of the first conductive line.
13. The semiconductor device of claim 12 , further comprising: a second dielectric layer over the first dielectric layer; and a via in the second dielectric layer, the via connected to an upper surface of the second conductive line, an upper surface of the first conductive line being covered by the second dielectric layer.
14. A semiconductor device comprising: a substrate; a dielectric layer over the substrate; a first conductive line in the dielectric layer, the first conductive line extending from an upper surface of the dielectric layer distal from the substrate into the dielectric layer by a first depth; and a first air gap in the dielectric layer and adjacent to a first sidewall of the first conductive line, the first air gap extending from the upper surface of the dielectric layer into the dielectric layer by a second depth smaller than the first depth, wherein a first width of the first air gap decreases as the first air gap extends towards the substrate, wherein a first portion of the dielectric layer is disposed between the first air gap and the first sidewall of the first conductive line, wherein the first portion of the dielectric layer extends from the upper surface of the dielectric layer to a first bottom of the first air gap.
15. The semiconductor device of claim 14 , wherein the first sidewall of the first conductive line is covered by the first portion of the dielectric layer.
16. The semiconductor device of claim 14 , further comprising a second air gap in the dielectric layer and adjacent to a second sidewall of the first conductive line, the second air gap extending from the upper surface of the dielectric layer into the dielectric layer by a third depth smaller than the first depth, wherein a second width of the second air gap decreases as the second air gap extends towards the substrate, wherein a second portion of the dielectric layer is disposed between the second air gap and the second sidewall of the first conductive line, wherein the second portion of the dielectric layer extends from the upper surface of the dielectric layer to a second bottom of the second air gap.
17. The semiconductor device of claim 16 , wherein a distance, measured between a first sidewall of the first portion of the dielectric layer facing away from the first conductive line and a second sidewall of the second portion of the dielectric layer facing away from the first conductive line, increases along a depth direction of the first air gap toward the substrate.
18. The semiconductor device of claim 14 , further comprising a second conductive line in the dielectric layer and laterally adjacent to the first conductive line, wherein the first air gap is between the first conductive line and the second conductive line, wherein a second portion of the dielectric layer is between the first air gap and the second conductive line, wherein a width of the second portion of the dielectric layer increases as the second portion of the dielectric layer extends toward the substrate.
19. The semiconductor device of claim 18 , wherein the first air gap is adjacent to a first sidewall of the second conductive line, wherein there is no air gap adjacent to a second opposing sidewall of the second conductive line.
20. The semiconductor device of claim 8 , wherein a width of the first portion of the first dielectric layer increase as the first portion of the first dielectric layer extends toward the substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 11, 2019
February 16, 2021
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