A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device, comprising: forming a circuit on a pad region of a substrate comprising a first cell region, the pad region, and a second cell region, which are successively arranged in a first direction; forming a stacked structure over the substrate on which the circuit is formed, the stacked structure including first to n th (n is a natural number greater than or equal to three) groups stacked on top of one another; partially patterning the pad region of the stacked structure and forming a first cell structure disposed in the first cell region, a second cell structure disposed in the second cell region, and a pad structure disposed in the pad region, the pad structure comprising a plurality of stepped structures, wherein the plurality of stepped structures comprise different stepped structures in different groups of the first to n th groups, wherein the pad structure comprises a fifth stepped structure including fifth pads stacked on top of one another and a line structure including lines stacked on top of one another, wherein the lines are electrically coupled to the fifth pads, respectively, and each of the fifth pads is electrically coupled to the first and second cell structures through each of the lines; forming one or more openings passing through the pad structure and exposing the circuit; and forming a first interconnection structure electrically coupling the fifth pads to the circuit through the openings so that the first and second cell structures are electrically coupled to the circuit.
2. The method of claim 1 , wherein forming the stacked structure comprises: forming the first group including first material layers and second material layers which are alternately stacked on top of one another; forming first slit insulating layers passing through the first group in the pad region and extending in the first direction; and forming the second to n th groups over the first group, each of the second to n th groups including first material layers and second material layers which are alternately stacked on top of one another.
3. The method of claim 2 , further comprising, after forming the pad structure, forming second slit insulating layers passing through the first to n th groups in the pad region and extending in a second direction intersecting with the first direction, the second slit insulating layers being coupled to the first slit insulating layers.
4. The method of claim 1 , wherein forming the pad structure comprises partially patterning the n th group of the stacked structure and forming a first stepped structure and a second stepped structure, and wherein: the first stepped structure includes first pads stacked on top of one another, the first pads contacting with the first cell structure and being electrically coupled to the n th group of the first cell structure; and the second stepped structure includes second pads stacked on top of one another, the second pads contacting with the second cell structure and being electrically coupled to the n th group of the second cell structure.
5. The method of claim 4 , further comprising forming a second interconnection structure electrically coupling the first pads to the second pads.
6. The method of claim 1 , wherein forming the pad structure comprises partially patterning the first to (n−1) th groups of the stacked structure and forming third stepped structures comprising third pads stacked on top of one another, the third pads being coupled in common to the second to (n−1) th groups of the first cell structure and the second to (n−1) th groups of the second cell structure.
7. The method of claim 6 , further comprising: forming a slit insulating layer extending in the first direction to traverse the third stepped structures so that the third pads of the third stepped structures are divided by the slit insulating layer; and forming a third interconnection structure electrically coupling, among the third pads of the third stepped structures that are divided by the slit insulating layer, third pads that are disposed at the same level, to each other.
8. The method of claim 1 , wherein forming the pad structure comprises: partially patterning the first to (n−1) th groups of the stacked structure and forming a fourth stepped structure and a sixth stepped structure, the fourth stepped structure comprising fourth pads stacked on top of one another and being electrically coupled to the first group of the first cell structure, the sixth stepped structure comprising sixth pads stacked on top of one another and being electrically coupled to the first group of the second cell structure.
9. The method of claim 8 , further comprising: forming a fourth interconnection structure electrically coupling the fourth pads to the sixth pads and coupling the fourth and sixth pads to the circuit through the openings.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 14, 2017
February 23, 2021
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