An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An imaging device, comprising: a first substrate; a contact disposed on the first substrate and including a first surface that faces the first substrate and a second surface opposite the first surface; a first insulation layer on sidewalls of the contact and including an opening that exposes the second surface of the contact; at least one bump pad including: a first metal layer disposed in the opening of the first insulation layer and electrically connected to the contact; and a second metal layer disposed in the opening of the first insulation layer and on the first metal layer; a second insulation layer on the first insulation layer and including an opening that exposes the second metal layer; a second substrate including at least one electrode; and a microbump electrically connecting the at least one bump pad to the at least one electrode and positioned in the opening in the second insulation layer, wherein the microbump includes a diffused portion of the second metal layer, and wherein the first substrate or the second substrate includes a pixel unit.
2. The imaging device according to claim 1 , wherein the microbump includes Sn-based solder and the first metal layer includes Co.
3. The imaging device according to claim 2 , wherein the at least one bump pad includes a plurality of bump pads with different diameters, and wherein the at least one electrode includes a plurality of electrodes corresponding to the plurality of bump pads.
4. The imaging device according to claim 3 , wherein the different diameters are different from each other according to an application of the plurality of electrodes to be connected.
5. The imaging device according to claim 1 , wherein a diameter of the microbump corresponds to a diameter of the at least one bump pad.
6. The imaging device according to claim 1 , wherein the at least one bump pad includes a third metal layer disposed in the opening of the first insulation layer, and wherein the first metal layer is on the third metal layer.
7. The imaging device according to claim 6 , wherein an average thickness of the first metal layer is 15 nm or thicker.
8. The imaging device according to claim 6 , wherein an average thickness of the third metal layer is 10 nm or thicker.
9. The imaging device according to claim 6 , wherein the third metal layer is formed of TiN, Ta, or TaN.
10. The imaging device according to claim 6 , wherein the second metal layer is formed of Cu, Co, Ni, Pd, Au, or Pt.
11. The imaging device according to claim 1 , wherein a surface of the second metal layer is coplanar with a surface of the first insulation layer.
12. The imaging device according to claim 1 , wherein the first insulation layer contacts the second surface of the contact.
13. The imaging device according to claim 1 , wherein the first substrate is the pixel unit and the second substrate is a logic chip that is connected by a chip on wafer (CoW) connection to the first substrate.
14. A method of manufacturing an imaging device, comprising: forming at least one contact on a first substrate, the at least one contact having a first surface that faces the first substrate and a second surface opposite the first surface; forming a first insulation layer on the at least one contact, the first insulation layer being in contact with sidewalls of the at least one contact; etching the first insulation layer to provide at least one first opening that exposes a portion of the at least one contact; forming at least one bump pad in the at least one first opening of the first insulation layer; forming a second insulation layer on the first insulation layer and the at least one bump pad; etching the second insulation layer to provide at least one second opening that exposes the at least one bump pad; and electrically connecting the at least one bump pad to an electrode of a second substrate by positioning a microbump connected to the electrode in the at least one second opening of the second insulation layer and by diffusing a portion of the at least one bump pad into the microbump, wherein the first substrate or the second substrate includes a pixel unit.
15. The method of claim 14 , wherein the forming the at least one bump pad includes: forming a first metal layer on the at least one contact in the at least one first opening; and forming a second metal layer on the first metal layer, wherein the diffused portion of the at least one bump pad includes the second metal layer.
16. The method of claim 15 , wherein the forming the second metal layer includes: forming a portion of the second metal layer in the at least one first opening of the first insulation layer according to a first deposition process; and forming a remaining portion of the second metal layer according to a second deposition process to fill the at least one first opening of the first insulation layer.
17. The method of claim 15 , the forming the at least one bump pad includes forming a third metal layer in the at least one first opening of the first insulation layer before forming the first and second metal layers.
18. The method of claim 17 , wherein the forming the at least one bump pad includes planarizing the first, second, and third metal layers such that a surface of the second metal layer is coplanar with a surface of the first insulation layer.
19. The method of claim 18 , wherein the second metal layer is diffused into the microbump such that a tip portion of the microbump extends beyond the upper surface of the first insulation layer while another portion of the microbump exists in a space between the upper surface of the first insulation layer and the electrode.
20. The method of claim 18 , wherein first insulation layer contacts the second surface of the at least one contact.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 7, 2016
February 23, 2021
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