Systems and methods for using a common fuse controller hardware design for different applications are described. A method includes specifying a first fuse map for a first system on a chip (SoC) and a second fuse map for a second SoC. The method further includes processing the first fuse map to generate a first hardware description language (HDL) file and processing the second fuse map to generate a second HDL file. The method further includes using a processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, implemented by a processor, related to a first system on a chip (SoC) and a second SoC, different from the first SoC, the method comprising: specifying a first fuse map for the first SoC; specifying a second fuse map for the second SoC; using the processor, processing the first fuse map to generate a first hardware description language (HDL) file based on the first fuse map; using the processor, processing the second fuse map to generate a second HDL file based on the second fuse map; and using the processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.
2. The method of claim 1 , wherein the specifying the first fuse map comprises specifying a first fuse region, and wherein the specifying the second fuse map comprises specifying a second fuse region.
3. The method of claim 2 , wherein each of the first fuse region and the second fuse region comprises a plurality of attribute types, wherein each of the plurality of attribute types is required for ensuring at least one of authenticity, confidentiality, or integrity for a respective fuse region.
4. The method of claim 3 , wherein the plurality of attribute types includes a first attribute type concerning any permissions associated with reading, writing, or programming of a respective fuse region by a processing unit or a hardware block associated with a respective SoC.
5. The method of claim 3 , wherein the plurality of attribute types includes a second attribute type concerning any permissions or timing associated with a loading of a respective fuse region to a destination.
6. The method of claim 3 , wherein the plurality of attribute types includes a third attribute type concerning any encoding associated with a respective fuse region.
7. The method of claim 3 , wherein the plurality of attribute types includes a fourth attribute type concerning any integrity protection method associated with a respective fuse region.
8. The method of claim 3 , wherein any value for each of the plurality of attribute types corresponds to a fixed value or a dynamic value assigned by a trusted entity.
9. A method, implemented by a processor, for generating hardware description for a first system on a chip (SoC) or a second SoC, different from the first SoC, the method comprising: specifying a first fuse map for the first SoC, wherein the first fuse map comprises a first plurality of fuse regions; specifying a second fuse map for the second SoC, wherein the second fuse map comprises a second plurality of fuse regions different from the first plurality of fuse regions; using the processor, processing the first fuse map to generate a first hardware description language (HDL) file corresponding to the first fuse map; using the processor, processing the second fuse map to generate a second HDL file corresponding to the second fuse map; using the processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output HDL file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output HDL file capturing behavior expressed in the second fuse map; and using the processor, synthesizing the first output HDL file to generate a first set of logic structures corresponding to the first SoC and synthesizing the second output HDL file to generate a second set of logic structures corresponding to the second output HDL file.
10. The method of claim 9 , wherein each of the first plurality of fuse regions and the second plurality of fuse regions comprises a plurality of attribute types, wherein each of the plurality of attribute types is required for ensuring at least one of authenticity, confidentiality, or integrity for a respective fuse region.
11. The method of claim 10 , wherein the plurality of attribute types includes a first attribute type concerning any permissions associated with reading, writing, or programming of a respective fuse region by a processing unit or a hardware block associated with a respective SoC.
12. The method of claim 10 , wherein the plurality of attribute types includes a second attribute type concerning any permissions or timing associated with a loading of a respective fuse region to a destination.
13. The method of claim 10 , wherein the plurality of attribute types includes a third attribute type concerning any encoding associated with a respective fuse region.
14. The method of claim 10 , wherein the plurality of attribute types includes a fourth attribute type concerning any integrity protection method associated with a respective fuse region.
15. The method of claim 10 , wherein any value for each of the plurality of attribute types corresponds to a fixed value or a dynamic value assigned by a trusted entity.
16. A system, including a processor, for processing fuse regions related to a first system on a chip (SoC) and a second SoC, different from the first SoC, the system configured to: receive a first fuse map for the first SoC; receive a second fuse map for the second SoC; using the processor, process the first fuse map to generate a first hardware description language (HDL) file based on the first fuse map; using the processor, process the second fuse map to generate a second HDL file based on the second fuse map; and using the processor, compile a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compile the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.
17. The system of claim 16 , wherein the first fuse map comprises a first fuse region, and wherein the second fuse map comprises a second fuse region.
18. The system of claim 17 , wherein each of the first fuse region and the second fuse region comprises a plurality of attribute types, wherein each of the plurality of attribute types is required for ensuring at least one of authenticity, confidentiality, or integrity for a respective fuse region.
19. The system of claim 18 , wherein the plurality of attribute types includes: (1) a first attribute type concerning any permissions associated with reading, writing, or programming of a respective fuse region by a processing unit or a hardware block associated with a respective SoC; (2) a second attribute type concerning any permissions or timing associated with a loading of a respective fuse region to a destination associated with a respective SoC; (3) a third attribute type concerning any encoding associated with a respective fuse region; and (4) a fourth attribute type concerning any integrity protection method associated with a respective fuse region.
20. The system of claim 17 , wherein any value for each of the plurality of attribute types corresponds to a fixed value or a dynamic value assigned by a trusted entity.
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October 2, 2019
March 2, 2021
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