Compensating offsets in buffers and related systems, methods, and devices

1. An apparatus, comprising: buffers, each of the buffers including an output and an offset adjustment input, each of the buffers controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input; control circuitry including sets of offset latches, the offset adjustment input of each of the buffers operably coupled to a different one of the sets of offset latches, each set of offset latches configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer; and fuses operably coupled to the control circuitry, the fuses configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

2. The apparatus of claim 1 , wherein each other set of offset latches that is outside of the subset are to be set to an offset adjustment code corresponding to zero offset adjustment.

3. The apparatus of claim 1 , wherein a number of the fuses is less than a product between a number of bits of the offset adjustment code and a number of the buffers.

4. The apparatus of claim 1 , wherein the fuses are configured to store sets of offset information, each set of offset information corresponding to a different set of offset latches of the subset of the sets of offset latches, each set of offset information including the offset adjustment code and latch selection information configured to enable the control circuitry to provide the offset adjustment code to its corresponding set of offset latches.

5. The apparatus of claim 4 , wherein: the sets of offset latches has an ordered sequence associated therewith, each set of offset latches having a position of the ordered sequence associated therewith; the sets of offset latches are operably coupled in series to serially shift offset adjustment codes provided thereto along the sets of offset latches in the ordered sequence; and the latch selection information includes a skip code indicating a number of sets of offset latches to skip in the ordered sequence to obtain the position of the ordered sequence associated therewith.

6. The apparatus of claim 5 , wherein the control circuitry further comprises: a shift register operably coupled to the fuses, the shift register configured to receive a clock signal, the shift register configured to serially provide bits of the sets of offset information responsive to cycles of the clock signal; and a counter circuit operably coupled to the shift register, the counter circuit configured to: receive the serially provided bits of the sets of offset information from the shift register; provide, to the sets of offset latches, a zero offset adjustment code a number of times that is responsive to the number of sets of offset latches indicated by the skip code; and provide, to the sets of offset latches, the offset adjustment code.

7. The apparatus of claim 6 , wherein the counter circuit includes: an output select counter configured to selectively switch an output of the counter circuit between an output of the shift register and a zero offset adjustment code generator; and a latch clock counter configured to provide a latch clock signal configured to selectively clock the sets of offset latches.

8. The apparatus of claim 7 , wherein the zero offset adjustment code generator includes a low power supply voltage potential level.

9. The apparatus of claim 4 , wherein: each of the sets of offset latches has an identification code associated therewith; and the latch selection information corresponding to each set of offset latches of the subset of the sets of offset latches includes the identification code associated with the set of offset latches corresponding to the latch selection information.

10. The apparatus of claim 9 , wherein the control circuitry further includes: a shift register configured to serially provide bits of the sets of offset information to an output of the shift register; and switch circuits, each switch circuit operably coupled between one of the sets of offset latches and the shift register, each switch circuit configured to operably couple the output of the shift register to the set of offset latches operably coupled thereto responsive to the identification code associated with the set of offset latches operably coupled thereto.

11. The apparatus of claim 1 , wherein: the apparatus includes a memory device; and the buffers include input buffers of the memory device.

12. An apparatus, comprising: input buffers including offset adjustment inputs, the input buffers configured to adjust direct current offsets of outputs of the input buffers responsive to offset adjustment codes provided to the offset adjustment inputs; fuses configured to store a subset of the offset adjustment codes that corresponds to non-zero offset adjustments; and control circuitry operably coupled to the fuses and the offset adjustment inputs of the input buffers, the control circuitry configured to provide the subset of the offset adjustment codes to the offset adjustment inputs of the corresponding input buffers.

13. The apparatus of claim 12 , wherein: the input buffers are associated with an ordered sequence, each input buffer associated with a position in the ordered sequence; the fuses are further configured to store skip codes associated with the offset adjustment codes, the skip codes configured to indicate numbers of input buffers, in the ordered sequence, between the input buffers corresponding to the subset of offset adjustment codes; and the control circuitry is configured provide the subset of the offset adjustment codes responsive to the skip codes.

14. The apparatus of claim 12 , wherein the control circuitry includes sets of offset latches operably coupled to the offset adjustment inputs of the input buffers, the sets of offset latches configured to provide the offset adjustment codes to the offset adjustment inputs of the input buffers.

15. The apparatus of claim 14 , wherein the sets of offset latches are operably coupled in series according to an ordered sequence of the input buffers to enable the offset adjustment codes to shift serially along the sets of offset latches to the sets of offset latches associated with the offset adjustment codes.

16. The apparatus of claim 15 , wherein the control circuitry further includes counter circuitry configured to selectively operably couple the sets of offset latches to a fuse output responsive to skip codes.

17. The apparatus of claim 12 , wherein: the input buffers are associated with identification codes; the fuses are further configured to store those of the identification codes that are associated with the input buffers corresponding to the subset of the offset adjustment codes; and the control circuitry is configured to provide the subset of the offset adjustment codes responsive to the identification codes.

18. A computing system, comprising: a memory device including: input buffers associated with an ordered sequence, the input buffers associated with positions in the ordered sequence, the input buffers including offset adjustment inputs, the input buffers configured to adjust direct current offsets of outputs of the input buffers responsive to offset adjustment codes provided to the offset adjustment inputs; fuses configured to store only a subset of the offset adjustment codes that corresponds to non-zero offset adjustments, the fuses further configured to store skip codes associated with the offset adjustment codes, the skip codes configured to indicate numbers of input buffers, in the ordered sequence, between the input buffers corresponding to the subset of offset adjustment codes; and control circuitry operably coupled to the fuses and the offset adjustment inputs of the input buffers, the control circuitry configured to provide the subset of the offset adjustment codes to the offset adjustment inputs of the corresponding input buffers responsive to the skip codes.

19. The computing system of claim 18 , wherein the input buffers are configured to buffer data signals at data input/output lines of the memory device.

20. The computing system of claim 18 , further comprising: one or more processors operably coupled to the memory device; one or more non-volatile data storage devices operably coupled to the one or more processors; one or more input devices operably coupled to the one or more processors; and one or more output devices operably coupled to the one or more processors.