Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device, the method comprising: alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate; forming a hole penetrating the mold structure; conformally forming on the substrate a second semiconductor layer filling the hole; and irradiating a laser onto the second semiconductor layer, wherein a sidewall of the mold structure being defined by the hole, wherein the sidewall has a slope relative to a top surface of the substrate, wherein forming the second semiconductor layer comprises forming on the substrate a first segment of the second semiconductor layer, and forming on the sidewall of the mold structure a second segment of the second semiconductor layer, and wherein the second segment has a slope relative to the top surface of the substrate.
2. The method of claim 1 , wherein forming the hole exposes the top surface of the substrate.
3. The method of claim 1 , wherein the irradiating the laser comprises: single-crystallizing the second semiconductor layer along crystallinity of the substrate; and single-crystallizing the first semiconductor layers along crystallinity of the second semiconductor layer that has been single-crystallized.
4. The method of claim 3 , wherein the single-crystallizing the second semiconductor layer comprises converting the second semiconductor layer from amorphous into single crystalline, and the single-crystallizing the first semiconductor layers comprises converting the first semiconductor layer from amorphous into single crystalline.
5. The method of claim 4 , wherein the substrate includes a single crystalline semiconductor material.
6. The method of claim 1 , wherein irradiating the laser comprises: causing the laser to increase temperature of the second semiconductor layer; and providing the first semiconductor layers with heat from the second semiconductor layer.
7. The method of claim 1 , wherein forming the second semiconductor layer comprises allowing the second semiconductor layer to cover the sidewall of the mold structure.
8. A method of manufacturing a semiconductor device, the method comprising: forming on a substrate a mold structure including a dielectric layer and a first semiconductor layer; forming a hole penetrating the mold structure; conformally forming on the substrate a second semiconductor layer filling the hole; and irradiating a laser onto the second semiconductor layer, wherein forming the hole comprises exposing a top surface of the substrate, wherein a sidewall of the mold structure being defined by the hole, wherein the sidewall has a slope relative to the top surface of the substrate, wherein forming the second semiconductor layer comprises forming on the substrate a first segment of the second semiconductor layer, and forming on the sidewall of the mold structure a second segment of the second semiconductor layer, and wherein the second segment has a slope relative to the top surface of the substrate.
9. The method of claim 8 , further comprising removing the second semiconductor layer.
10. The method of claim 9 , wherein removing the second semiconductor layer comprises performing a wet etching process to remove the second semiconductor layer.
11. The method of claim 8 , wherein irradiating the laser comprises: causing the laser to increase temperature of the second semiconductor layer; and providing the first semiconductor layer with heat from the second semiconductor layer.
12. A method of manufacturing a semiconductor device, the method comprising: stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate; forming a hole penetrating the mold structure, wherein forming the hole comprises forming a sidewall of the mold structure, the sidewall being defined by the hole, and forming a semiconductor pattern on each of the first semiconductor layers, the semiconductor pattern extending in a first direction; forming on the substrate a second semiconductor layer filling the hole; irradiating a laser onto the second semiconductor layer; forming a first conductive line on the sidewall of the mold structure; forming on the semiconductor pattern a second conductive line that extends in a second direction intersecting the first direction; and forming a data storage element connected to the semiconductor pattern.
13. The method of claim 12 , wherein the semiconductor pattern comprises: a first impurity region connected to the second conductive line; and a second impurity region connected to the data storage element.
14. The method of claim 12 , wherein forming the first conductive line comprises: forming a preliminary conductive line on the sidewall of the mold structure; forming on the mold structure a mask pattern including an opening; and removing the preliminary conductive line exposed to the opening.
15. The method of claim 14 , wherein forming the preliminary conductive line comprises: conformally forming a barrier layer on the sidewall of the mold structure; conformally forming a conductive layer on the barrier layer; and etching the barrier layer and the conductive layer.
16. The method of claim 12 , further comprising forming a second dielectric layer completely filling the hole.
17. The method of claim 16 , further comprising performing a wet etching process to remove the second semiconductor layer and the second dielectric layer.
18. The method of claim 16 , wherein irradiating the laser comprises liquefying the second semiconductor layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 2, 2019
March 9, 2021
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.