In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer including a first semiconductor as a major component, an i-type semiconductor layer including a second semiconductor as a major component and a p-type semiconductor layer including a third semiconductor as a major component. The second semiconductor contains a corundum-structured oxide semiconductor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: an n-type semiconductor layer comprising a first semiconductor as a major component; an i-type semiconductor layer comprising a second semiconductor as a major component; and a p-type semiconductor layer comprising a third semiconductor as a major component, wherein the i-type semiconductor layer has a first carrier concentration, wherein the n-type semiconductor layer has a second carrier concentration that is larger than the first carrier concentration, wherein the p-type semiconductor layer has a third carrier concentration that is larger than the first carrier concentration, wherein the second semiconductor comprises a corundum-structured oxide semiconductor, and wherein a breakdown voltage of the semiconductor device is 400 V or more.
2. The semiconductor device according to claim 1 , wherein the i-type semiconductor layer is arranged on the n-type semiconductor layer, and wherein the p-type semiconductor layer is arranged on the i-type semiconductor layer to form a PiN structure.
3. The semiconductor device according to claim 1 , wherein the first semiconductor comprises at least one metal selected from among aluminum, indium, and gallium.
4. The semiconductor device according to claim 1 , wherein the first semiconductor comprises gallium.
5. The semiconductor device according to claim 1 , wherein the third semiconductor comprises a d-block metal in the periodic table.
6. The semiconductor device according to claim 1 , wherein the second semiconductor comprises a p-block metal in the periodic table.
7. The semiconductor device according to claim 1 , wherein the second semiconductor comprises a d-block metal in the periodic table.
8. The semiconductor device according to claim 1 , wherein the second semiconductor comprises at least one metal selected from among aluminum, indium, and gallium.
9. The semiconductor device according to claim 1 , further comprising: a reduced surface field (RESURF) region.
10. The semiconductor device according to claim 1 , further comprising: a guard ring.
11. The semiconductor device according to claim 1 , wherein the semiconductor device is a diode.
12. The semiconductor device according to claim 1 , wherein the semiconductor device is a power device.
13. A semiconductor device comprising: an n-type semiconductor layer comprising a first semiconductor as a major component; an i-type semiconductor layer comprising a second semiconductor as a major component; and a p-type semiconductor layer comprising a third semiconductor as a major component, wherein the i-type semiconductor layer has a first carrier concentration, wherein the n-type semiconductor layer has a second carrier concentration that is larger than the first carrier concentration, wherein the p-type semiconductor layer has a third carrier concentration that is larger than the first carrier concentration, wherein each of the first semiconductor, the second semiconductor and the third semiconductor comprises a corundum-structured oxide semiconductor, and wherein a breakdown voltage of the semiconductor device is 400 V or more.
14. A semiconductor device comprising: an n-type semiconductor layer comprising a first semiconductor as a major component; an i-type semiconductor layer comprising a second semiconductor as a major component; and a p-type semiconductor layer comprising a third semiconductor as a major component, wherein the i-type semiconductor layer has a first carrier concentration, wherein the n-type semiconductor layer has a second carrier concentration that is larger than the first carrier concentration, wherein the p-type semiconductor layer has a third carrier concentration that is larger than the first carrier concentration, wherein the third semiconductor comprises a corundum-structured oxide semiconductor, and wherein a breakdown voltage of the semiconductor device is 400 V or more.
15. The semiconductor device according to claim 13 , wherein the i-type semiconductor layer is arranged on the n-type semiconductor layer, and wherein the p-type semiconductor layer is arranged on the i-type semiconductor layer to from a PiN structure.
16. The semiconductor device according to claim 13 , wherein the second semiconductor comprises at least one metal selected from among aluminum, indium, and gallium.
17. The semiconductor device according to claim 13 , wherein the i-type semiconductor layer is 10 μm or less in thickness.
18. The semiconductor device according to claim 13 , wherein the i-type semiconductor layer comprises a carrier concentration that is 1.0×10 16 /cm 3 or more.
19. The semiconductor device according to claim 14 , wherein the third semiconductor comprises a d-block metal in the periodic table.
20. The semiconductor device according to claim 14 , wherein the third semiconductor comprises α-Ga 2 O 3 or a mixed crystal of α-Ga 2 O 3 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 23, 2018
March 9, 2021
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