A display may have an array of pixels arranged in rows and columns. The pixels may be organic light-emitting diode pixels that each include an organic light-emitting diode and thin-film transistor circuitry for controlling the diode or may be other suitable display pixels. The pixels may form an active area of the display that displays images. Display driver circuitry may be provided in an inactive border area of the display. The display may include vertical gate lines. The display may also include data lines. The data lines may include vertical data line portions and orthogonal horizontal data line portions coupled to the vertical data line portions with vias. During operation, data from the display driver circuitry may be provided to rows of the pixels using the data lines while the vertical gate lines supply control signals to columns of the pixels.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A display, comprising: display driver circuitry; a plurality of pixels organized in rows and columns; a plurality of gate lines extending along a first direction, each of which is associated with a respective one of the columns of pixels, wherein the plurality of gate lines are formed from a first metal layer, and a dielectric layer is formed over the first metal layer; and a plurality of data lines, each of which has a first portion that is associated with a respective one of the rows of pixels and extends along a second direction which is orthogonal to the first direction, and each of which has a second portion that extends from the display driver circuitry towards a respective one of the first portions, wherein the second portions are formed from a second metal layer that is formed over the dielectric layer, wherein the first portions are formed from a third metal layer that is separated from the second metal layer by an additional dielectric layer, and wherein a given second portion of the second portions is coupled to a given pixel of the plurality of pixels via a corresponding first portion of the first portions, a given gate line of the plurality of gate lines is coupled to the given pixel, and the given second portion is formed over the given gate line with an offset.
2. The display defined in claim 1 further comprising: vias, wherein each via couples one of the second portions to a respective one of the first portions.
3. The display defined in claim 2 further comprising: a substrate having one or more edges, wherein the display driver circuitry is disposed along a given one of the edges, and wherein the display driver circuitry supplies image data signals to the data lines and gate line signals to the gate lines.
4. The display defined in claim 1 , wherein the pixels comprise subpixels that are arranged along the first direction.
5. The display defined in claim 1 , wherein each of the pixels comprise red, green, and blue subpixels and wherein each gate line in a given column of the pixels spans the red, green, and blue subpixels of each of the pixels in that column of pixels.
6. The display defined in claim 1 , wherein each pixel includes first, second, and third subpixels, wherein the first, second, and third subpixels are arranged along the first direction, and wherein at least two of the gate lines in each column of the pixels are configured to control the red, green, and blue subpixels of each of the pixels in that column of pixels.
7. The display defined in claim 6 , wherein the first portions are formed from a third metal layer, and wherein the first, second, and third subpixels of each pixel include respective first, second, and third light-emitting diodes.
8. The display defined in claim 1 further comprising: vias, wherein each via couples one of the second portions to a respective one of the first portions and wherein the pixels comprise organic light-emitting diode pixels.
9. The display defined in claim 1 further comprising: vias, wherein each via couples one of the second portions to a respective one of the first portions and wherein the pixels comprise liquid crystal display pixels.
10. The display defined in claim 1 , wherein at least two of the gate lines are arranged in each of the columns of pixels.
11. The display defined in claim 1 , wherein the pixels include thin-film transistors with transistor gates and wherein the transistor gates are formed from portions of the first metal layer.
12. A display, comprising: pixels organized in rows and columns, a given pixel of the pixels having a first subpixel of a first color and a second subpixel of a second color; gate lines, wherein each of the gate lines is configured to control a respective one of the columns of pixels, wherein at least two gate lines of the gate lines are both coupled to the first subpixel and at least the two gate lines are both coupled to the second subpixel, and wherein at least the two gate lines overlap each of the first and second subpixels and are configured to control each of the first and second subpixels; and data lines configured to load data into the rows of pixels, wherein each data line has a first data line portion extending along with a respective one of the rows of pixels and has a second data line portion extending orthogonally to the first data line portion.
13. The display defined in claim 12 further comprising vias, wherein each via couples a respective one of the first data line portions to a respective one of the second data line portions.
14. The display defined in claim 12 further comprising display driver circuitry, wherein the display driver circuitry is coupled to the gate lines and the first data line portions.
15. The display defined in claim 14 , wherein the display driver circuitry is configured to provide data to the pixels over the data lines while controlling the pixels using the gate lines and wherein each pixel in each column of pixels is coupled to at least two corresponding gate lines of the gate lines.
16. The display defined in claim 14 , wherein each pixel in each column of pixels is coupled to a respective set of at least two corresponding gate lines of the gate lines.
17. A display, comprising: organic light-emitting diode pixels organized in row and columns, each pixel including a respective organic light-emitting diode; display driver circuitry; gate lines coupled to the display driver circuitry, wherein the gate lines extend along the columns of the organic light-emitting diode pixels; and data lines each of which has a first data line portion and a second data line portion that extends orthogonally to the first data line portion between the display driver circuitry and a respective one of the first data line portions, wherein each of the first data line portions is coupled to a respective row of the organic light-emitting diode pixels, wherein the display driver circuitry is configured to provide data to the organic light-emitting diode pixels over the data lines while controlling the organic light-emitting diode pixels using the gate lines, wherein the organic light-emitting diode pixels in each column of the columns of pixels are each coupled to at least three corresponding gate lines of the gate lines, and wherein a first gate line in the at least three corresponding gate lines is configured to access each pixel in a given column of the columns of pixels, a second gate line in the at least three corresponding gate lines is configured to access each pixel in the given column, and a third gate line in the at least three corresponding gate lines is configured to access each pixel in the given column.
18. The display defined in claim 17 further comprising vias, wherein each via couples a respective one of the first data line portions to a respective one of the second data line portions.
19. The display defined in claim 17 , wherein the organic light-emitting diode pixels in each column of the columns of pixels are each coupled to at least four corresponding gate lines of the gate lines.
20. The display defined in claim 1 , wherein each of the second portions extends along the first direction, and the third metal layer is formed between the first metal layer and the second metal layer.
21. The display defined in claim 12 , wherein a third gate line of the gate lines is coupled to the first subpixel and coupled to the second subpixel, and wherein the third gate line overlaps each of the first and second subpixels and is configured to control each of the first and second subpixels.
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August 22, 2018
March 16, 2021
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