Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor device, comprising: etching a stack of alternating channel and sacrificial layers to form a plurality of fins, wherein a depth of said etching is controlled by a signal layer embedded in a substrate under the stack; forming bottom spacers on the signal layer, from the same material as the signal layer, by filling in recesses between the plurality of fins, such that the bottom spacers and the signal layer merge into a single structure having a ‘u’-shaped cross-section, wherein the signal layer has a width that extends underneath one fin of the plurality of fins and does not extend underneath neighboring fins of the plurality of fins; forming source and drain regions on ends of the channel layers; etching away the sacrificial layers; and forming a gate stack over and between the channel layers.
2. The method of claim 1 , further comprising forming the substrate by forming a plurality of signal layer pads on a base semiconductor layer and forming additional semiconductor material over the signal layer pads, wherein the signal layer pads make up the embedded signal layer.
3. The method of claim 2 , wherein forming the plurality of signal layer pads comprises patterning a layer of signal material on a surface of the base semiconductor layer, with gaps between adjacent signal layer pads.
4. The method of claim 3 , wherein forming the additional semiconductor material over the signal layer pads comprises epitaxially growing the additional semiconductor material from exposed portions of the base semiconductor layer between the signal layer pads to completely enclose the signal layer pads.
5. The method of claim 2 , wherein the signal layer pads have a width that is greater a width of the fins.
6. The method of claim 1 , further comprising detecting exposure of the signal layer by the etch of the stack and halting the etch after said detection.
7. The method of claim 1 , wherein the bottom spacers contact the signal layer to form a structure under at least one of the fins that has a u-shaped cross-section.
8. The method of claim 1 , wherein the bottom spacers have a top surface that has a height that is the same as a height of a top surface of the substrate.
9. The method of claim 1 , wherein a thickness of the signal layer is between 5 nm and 20 nm.
10. The method of claim 6 , wherein detecting the exposure of the signal layer comprises optical spectrometry.
11. The method of claim 6 , wherein detecting the exposure of the signal layer comprises laser endpoint detection.
12. A method of forming a semiconductor device, comprising: forming a plurality of signal layer pads on a base semiconductor layer; epitaxially growing additional semiconductor material from exposed portions of the base semiconductor layer between the signal pads to completely enclose the signal layer pads and to form a substrate with an embedded signal layer; forming a stack of alternating channel and sacrificial layers on the substrate; anisotropically etching the stack to form a plurality of fins, wherein each signal layer pad has a width that extends underneath a respective fin of the plurality of fins and does not extend underneath neighboring fins of the plurality of fins; detecting exposure of the signal layer pads by the anisotropic etch; halting the anisotropic etch responsive to the detection of the exposure of the signal layer; depositing dielectric to fill in recesses between the fins to contact the signal layer pads to form a structure under at least one of the plurality of fins that has a u-shaped cross-section; forming source and drain regions on sidewalls of the channel layers; forming inner spacers on ends of the sacrificial layers; etching away the sacrificial layers; and forming a gate stack over and between the channel layers.
13. The method of claim 12 , wherein forming the signal layer pads comprises patterning a layer of signal material on a surface of the base semiconductor layer, with gaps between adjacent signal layer pads.
14. The method of claim 13 , wherein the signal layer pads have a width that is greater than a width of the fins.
15. The method of claim 13 , wherein the dielectric material formed in the recesses, between the plurality of fins, has a top surface with a height that is the same as a height of a top surface of the substrate.
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October 11, 2018
March 23, 2021
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