Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a Physical layer (PHY) block comprising a plurality of PHY Physical Interface for PCI Express (PIPE) registers; a Media Access Control layer (MAC) block comprising a plurality of MAC PIPE registers; and a PHY/MAC interface to interface the PHY block and the MAC block, the PHY/MAC interface comprising: a first set of wires to transfer a plurality of register commands between the PHY block and the MAC block, at least some of the plurality of register commands comprising command, address and data to be transferred via the first set of wires over a plurality of clock cycles; and a second set of wires dedicated to transfer datapath signals between the PHY block and the MAC block, wherein: in a first mode, the PHY block is to send data and a PCLK to the MAC block; and in a second mode, the PHY block is to send data and a recovered clock to the MAC block.
2. The apparatus of claim 1 , wherein the PHY block comprises an elastic buffer, the elastic buffer to be used in a PIPE mode.
3. The apparatus of claim 1 , wherein the first mode comprises a PIPE mode.
4. The apparatus of claim 1 , wherein the second mode comprises a serialization and deserialization (SERDES) mode.
5. The apparatus of claim 1 , wherein the plurality of PHY PIPE registers comprises an 8-bit register.
6. The apparatus of claim 1 , further comprising an address space, wherein the plurality of PHY PIPE registers and the plurality of MAC PIPE registers are mapped into the address space.
7. The apparatus of claim 1 , wherein the plurality of register commands comprises write commands, read commands and completions.
8. The apparatus of claim 1 , wherein the PHY block is to support Rx/Tx configurable pairs.
9. The apparatus of claim 8 , wherein the Rx/Tx configurable pairs are configured as{Rx, Tx}, {Rx, Rx}, {Tx, Tx} or {Tx, Rx}.
10. The apparatus of claim 1 , wherein the PHY/MAC interface is to support DisplayPort.
11. The apparatus of claim 1 , wherein the PHY block is selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.
12. An apparatus comprising: a Media Access Control layer (MAC) block comprising a plurality of MAC Physical Interface for PCI Express (PIPE) registers; and a PHY/MAC interface to interface a Physical layer (PHY) block and the MAC block, the PHY/MAC interface comprising: a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block; wherein: the low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner; and in a first mode, the MAC block is to receive data and a PCLK from the PHY block; and in a second mode, the MAC block is to receive data and a recovered clock from the PHY block.
13. The apparatus of claim 12 , wherein the first mode comprises a PIPE mode.
14. The apparatus of claim 12 , wherein the second mode comprises a serialization and deserialization (SERDES) mode.
15. The apparatus of claim 12 , wherein the plurality of MAC PIPE registers comprises an 8-bit register.
16. The apparatus of claim 12 , further comprising an address space, wherein the plurality of MAC PIPE registers are mapped into the address space.
17. An apparatus comprising: a Physical layer (PHY) block comprising a plurality of PHY Physical Interface for PCI Express (PIPE) registers to interface with a Media Access Control layer (MAC) block comprising a plurality of MAC PIPE registers; and a PHY/MAC interface to interface the PHY block and the MAC block, the PHY/MAC interface comprising: a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block to transfer a plurality of register commands between the PHY block and the MAC block, at least some of the plurality of register commands comprising command, address and data to be transferred over a plurality of clock cycles; wherein the PHY block is selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.
18. The apparatus of claim 17 , wherein in the PIPE mode, the PHY block is to send data and a PCLK to the MAC block.
19. The apparatus of claim 17 , wherein in the SERDES mode, the PHY block is to send data and a recovered clock to the MAC block.
20. An apparatus comprising: a Physical layer (PHY) block comprising a plurality of PHY registers; a Media Access Control layer (MAC) block comprising a plurality of MAC registers; and a PHY/MAC interface to interface the PHY block and the MAC block, the PHY/MAC interface comprising: a first set of wires to transfer a plurality of register commands between the PHY block and the MAC block, at least some of the plurality of register commands comprising command, address and data to be transferred via the first set of wires over a plurality of clock cycles; and a second set of wires dedicated to transfer datapath signals between the PHY block and the MAC block, wherein: in a first mode, the PHY block is to send data and a PCLK to the MAC block; and in a second mode, the PHY block is to send data and a recovered clock to the MAC block.
21. The apparatus of claim 20 , wherein the PHY block is selectively configurable to implement a first architecture when operating in the first mode and a serialization and deserialization (SERDES) architecture when operating in the second mode.
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February 26, 2020
March 30, 2021
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