A power supply circuit includes a voltage boosting circuit for boosting a supplied first power supply voltage to a second power supply voltage used in a drive circuit of a display device, a capacitor provided between a power supply wiring for outputting the second power supply voltage and a ground, a logic circuit for outputting a high-level signal when the first power supply voltage and a supplied first control signal are at a high level, a delay circuit for outputting a signal obtained by delaying an output signal of the logic circuit as a second control signal used for an operation control of the drive circuit, and a resistor provided between an input terminal of the delay circuit and the ground. The power supply circuit may include a first diode on the power supply wiring, or may include a second diode having an anode terminal connected to an output terminal of the second control signal and a cathode terminal connected to the input terminal of the delay circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A power supply circuit comprising: a voltage boosting circuit configured to boost a supplied first power supply voltage to a second power supply voltage used in a drive circuit of a display device; a capacitor provided between a power supply wiring for outputting the second power supply voltage and a ground; a logic circuit configured to output a high-level signal when the first power supply voltage and a supplied first control signal are at a high level; a delay circuit configured to output a signal obtained by delaying an output signal of the logic circuit as a second control signal used for an operation control of the drive circuit; and a resistor provided between an input terminal of the delay circuit and the ground.
2. The power supply circuit according to claim 1 , further comprising a first diode on the power supply wiring.
3. The power supply circuit according to claim 1 , further comprising a second diode having an anode terminal connected to an output terminal of the second control signal and a cathode terminal connected to the input terminal of the delay circuit.
4. The power supply circuit according to claim 1 , further comprising a reset IC in a later stage of the delay circuit.
5. The power supply circuit according to claim 1 , wherein the logic circuit includes a switch having one terminal to which one of the first power supply voltage and the first control signal is supplied, another terminal connected to the input terminal of the delay circuit, and a control terminal to which another of the first power supply voltage and the first control signal is supplied.
6. The power supply circuit according to claim 5 , wherein the switch is a bipolar transistor having one conduction terminal to which one of the first power supply voltage and the first control signal is supplied, another conduction terminal connected to the input terminal of the delay circuit, and a control terminal to which another of the first power supply voltage and the first control signal is supplied.
7. The power supply circuit according to claim 5 , wherein the switch is a MOS transistor having one conduction terminal to which one of the first power supply voltage and the first control signal is supplied, another conduction terminal connected to the input terminal of the delay circuit, and a control terminal to which another of the first power supply voltage and the first control signal is supplied.
8. The power supply circuit according to claim 1 , wherein the logic circuit includes an AND circuit configured to obtain a logical product of the first power supply voltage and the first control signal to supply the logical product to the input terminal of the delay circuit.
9. The power supply circuit according to claim 1 , wherein the logic circuit includes: an AND circuit configured to obtain a logical product of the first power supply voltage and the first control signal; and a switch having one terminal to which one of the first power supply voltage and the first control signal is supplied, another terminal connected to the input terminal of the delay circuit, and a control terminal to which the logical product is supplied.
10. The power supply circuit according to claim 1 , wherein the delay circuit includes: a resistor provided on a signal wiring for connecting an input terminal and an output terminal; and a capacitor provided between the signal wiring and the ground.
11. The power supply circuit according to claim 1 , wherein the delay circuit includes a reset IC configured to delay an input signal to output a delayed signal.
12. A display device comprising: a display panel including scanning lines and pixels; a scanning line drive circuit configured to drive the scanning lines; the power supply circuit according to claim 1 ; and a signal generation circuit configured to output a discharge signal having a discharge pulse to the scanning line drive circuit based on the second power supply voltage, when the second control signal indicates an operation stop.
13. The display device according to claim 12 , wherein the display panel is a liquid crystal panel.
14. The display device according to claim 13 , wherein a thin film transistor included in the liquid crystal panel is formed using an oxide semiconductor.
15. The display device according to claim 14 , wherein the oxide semiconductor is indium gallium zinc oxide.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 5, 2019
March 30, 2021
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