A capacitance-to-digital converter and an associated method and computer program product are provided that have an extended measurement range. A capacitance-to-digital converter includes first and second capacitors with the second capacitor being configured to measure a change in a value. The capacitance-to-digital converter also includes first and second switches switchably connecting the first and second capacitors, respectively, to a reference voltage while the first and second switches are in a first position such that charge is stored by the first and second capacitors in response to the reference voltage. The capacitance-to-digital converter further includes a saturation detector configured to detect the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor and, in response, causing the first and second switches to switch to a second position while continuing to measure the change in the value with the charge stored by the second capacitor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A capacitance-to-digital converter comprising: first and second capacitors, wherein the second capacitor is configured to measure a change in charge stored by the second capacitor, wherein the change in charge is representative of a corresponding change in a value; first and second switches switchably connecting the first and second capacitors, respectively, to a reference voltage while the first and second switches are in a first position such that charge is stored by the first and second capacitors in response to the reference voltage; and a saturation detector configured to detect the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor and, in response to detecting the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor, causing the first and second switches to switch to a second position while continuing to measure the change in the value with the charge stored by the second capacitor.
2. The capacitance-to-digital converter according to claim 1 further comprising a processor configured to differently determine a measure of the value depending upon whether the first and second switches are in the first or second position.
3. The capacitance-to-digital converter according to claim 1 further comprising a processor configured to: determine a measure of the value based upon a ratio of the charge stored by the second capacitor to the charge stored by the first capacitor in an instance in which the first and second switches are in the first position; and determine the measure of the value based upon a ratio of the charge stored by the first capacitor to the charge stored by the second capacitor in an instance in which the first and second switches are in the second position.
4. The capacitance-to-digital converter according to claim 1 wherein the saturation detector is configured to: detect, while the first and second switches are in the second position, the charge stored by the first capacitor equaling or exceeding the charge stored by the second capacitor; and in response to detecting the charge stored by the first capacitor equaling or exceeding the charge stored by the second capacitor, cause the first and second switches to switch to the first position while continuing to measure the change in the charge stored by the second capacitor as representative of the corresponding change in the value.
5. The capacitance-to-digital converter according to claim 1 wherein the saturation detector is configured to detect an output of the capacitance-to-digital converter being in saturation in response to the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor.
6. The capacitance-to-digital converter according to claim 1 further comprising third and fourth switches, wherein the third and fourth switches are configured to: while the first and second switches are in the first position, switchably connect the first capacitor to the reference voltage with the third switch and switchably connect the second capacitor to the input voltage with the fourth switch; and while the first and second switches are in the second position, switchably connect the second capacitor to the reference voltage with the third switch and switchably connect the first capacitor to the input voltage with the fourth switch.
7. The capacitance-to-digital converter according to claim 6 further comprising an amplifier to which the first and second capacitors are switchably connected such that, while an output of the amplifier is negative, the output of the amplifier is increased based upon the charge stored by a respective one of the first and second capacitors that is connected to the reference voltage by the fourth switch and independent of the charge stored by a respective one of the first and second capacitors that is connected to the reference voltage by the third switch and, while the output of the amplifier is positive, the output of the amplifier is decreased based upon a difference between the charges stored by the first and second capacitors.
8. The capacitance-to-digital converter according to claim 7 further comprising: a latch circuit configured to generate the output of the capacitance-to-digital converter in the form of a digital signal based upon the output of the amplifier; and a processor configured to determine a measure of the value based upon a ratio of a number of clock cycles having a predefined value to a total number of clock cycles within a measurement period.
9. The capacitance-to-digital converter according to claim 8 wherein the saturation detector is configured to detect the output of the capacitance-to-digital converter being in saturation in an instance in which the digital signal has the predefined value throughout the measurement period.
10. A method comprising: storing charge with first and second capacitors of a capacitance-to-digital converter while first and second switches are in a first position so as to connect the first and second capacitors, respectively, with a reference voltage; measuring a change in charge stored by the second capacitor, wherein the change in charge is representative of a corresponding change in a value; detecting the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor; and in response to detecting the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor, causing the first and second switches to switch to a second position while continuing to measure the change in the charge stored by the second capacitor as representative of the corresponding change in the value.
11. The method according to claim 10 further comprising differently determining a measure of the value depending upon whether the first and second switches are in the first or second position.
12. The method according to claim 11 wherein differently determining the measure of the value comprises: determining the measure of the value based upon a ratio of the charge stored by the second capacitor to the charge stored by the first capacitor in an instance in which the first and second switches are in the first position; and determining the measure of the value based upon a ratio of the charge stored by the first capacitor to the charge stored by the second capacitor in an instance in which the first and second switches are in the second position.
13. The method according to claim 10 further comprising: while the first and second switches are in the second position, detecting the charge stored by the first capacitor equaling or exceeding the charge stored by the second capacitor; and in response to detecting the charge stored by the first capacitor equaling or exceeding the charge stored by the second capacitor, causing the first and second switches to switch to the first position while continuing to measure the change in the charge stored by the second capacitor as representative of the corresponding change in the value.
14. The method according to claim 10 wherein detecting the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor comprises detecting an output of the capacitance-to-digital converter being in saturation.
15. The method according to claim 10 further comprising: while the first and second switches are in the first position, switchably connecting the first capacitor to the reference voltage with a third switch and switchably connecting the second capacitor to the reference voltage with a fourth switch; and while the first and second switches are in the second position, switchably connecting the second capacitor to the reference voltage with the third switch and switchably connecting the first capacitor to the reference voltage with the fourth switch.
16. The method according to claim 10 further comprising switchably connecting the first and second capacitors to an amplifier such that, while an output of the amplifier is negative, the output of the amplifier is increased based upon the charge stored by a respective one of the first and second capacitors that is connected to the reference voltage by the fourth switch and independent of the charge stored by a respective one of the first and second capacitors that is connected to the reference voltage by the third switch and, while the output of the amplifier is positive, the output of the amplifier is decreased based upon a difference between the charges stored by the first and second capacitors.
17. The method according to claim 16 further comprising generating the output of the capacitance-to-digital converter in the form of a digital signal based upon the output of the amplifier; and determining a measure of the value based upon a ratio of a number of clock cycles having a predefined value to a total number of clock cycles within a measurement period.
18. The method according to claim 17 wherein detecting the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor comprises detecting the output of the capacitance-to-digital converter being in saturation in an instance in which the digital signal has the predefined value throughout the measurement period.
19. A computer program product configured to control a capacitance-to-digital converter comprising first and second capacitors switchably connected to a reference voltage with first and second switches, respectively, that are in a first position, wherein the second capacitor is configured to measure a change in a value with a corresponding change in charge stored by the second capacitor, and wherein the capacitance-to-digital converter further comprises a saturation detector configured to detect a charge stored by the second capacitor equaling or exceeding a charge stored by the first capacitor, the computer program product comprising at least one non-transitory computer-readable storage medium having computer-executable program code instructions stored therein, the computer-executable program code instructions comprising program code instructions configured to: control the first and second switches to switch to a second position, different than the first position, in response to detecting that the charge stored by the second capacitor equals or exceeds the charge stored by the first capacitor.
20. The computer program product according to claim 19 wherein the computer-executable program code instructions further comprise program code instructions configured to: determine a measure of the value based upon a ratio of the charge stored by the second capacitor to the charge stored by the first capacitor in an instance in which the first and second switches are in the first position; and determine the measure of the value based upon a ratio of the charge stored by the first capacitor to the charge stored by the second capacitor in an instance in which the first and second switches are in the second position.
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April 23, 2020
March 30, 2021
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