SRAM structure

1. An SRAM structure comprising: a substrate; a first active region, a second active region, a third active region and a fourth active region disposed on the substrate, wherein the first active region, the second active region, the third active region and the fourth active region are parallel to each other, do not connect to each other structurally and are arranged from left to right in a sequence of the third active region, the first active region, the second active region and the fourth active region; a first gate line disposed on the substrate, wherein the first gate line comprises a first part, a second part and a third part, the first part and the third part are perpendicular to the first active region, the second part is parallel to the first active region, the first part covers the first active region, the second active region and the fourth active region, the third part covers the fourth active region, the second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part; a second gate line disposed on the substrate, wherein the second gate line comprises a fourth part, a fifth part and a sixth part, the fourth part and the sixth part are perpendicular to the first active region, the fifth part is parallel to the first active region, the fourth part covers the first active region, the second active region and the third active region, the sixth part covers the third active region, and the fifth part covers the insulating region between the first active region and the third active region and contacts the fourth part and the sixth part; a fifth active region; a sixth active region, wherein the fifth active region and the sixth active region are parallel to the first active region, the third active region is disposed between the first active region and the fifth active region, the fourth active region is disposed between the sixth active region and the second active region, and the first active region, the second active region, the third active region, the fourth active region, the fifth active region and the sixth active region do not connect to each other structurally; a third gate line covering the sixth active region; a fourth gate line covering the sixth active region; a fifth gate line covering the fifth active region; and a sixth gate line covering the fifth active region.

2. The SRAM structure of claim 1 , wherein the first part and the third part do not connect to each other structurally, and the fourth part and the sixth part do not connect to each other structurally.

3. The SRAM structure of claim 1 , wherein: a first pull down transistor and a second pull down transistor are disposed in the third active region; a third pull down transistor and a fourth pull down transistor are disposed in the fourth active region; a first pull up transistor is disposed in the first active region; and a second pull up transistor is disposed in the second active region.

4. The SRAM structure of claim 3 , wherein: a first passing gate transistor and a second passing gate transistor are disposed in the sixth active region; and a third passing gate transistor and a fourth passing gate transistor are disposed in the fifth active region.

5. The SRAM structure of claim 4 , wherein the first pull up transistor, the second pull up transistor, the first pull down transistor, the second pull down transistor, the third pull down transistor and the fourth pull down transistor form two cross-coupled inverters.

6. The SRAM structure of claim 5 , wherein the first passing gate transistor and the third passing gate transistor serve as a first terminal of the two cross-coupled inverters, and the second passing gate transistor and the fourth gate transistor serve as a second terminal of the two cross-coupled inverters.

7. The SRAM structure of claim 3 , wherein the first part overlapping the fourth active region serves as a gate of the fourth pull down transistor, and the first part overlapping the first active region serves as a gate of the first pull up transistor.

8. The SRAM structure of claim 7 , wherein a structure of the second part is the same as a structure of the gate of the fourth pull down transistor.

9. The SRAM structure of claim 7 , wherein a structure of the second part is the same as a structure of the gate of the first pull up transistor.

10. An SRAM structure comprising: a substrate; a fifth active region, a third active region, a first active region, a second active region, a fourth active region and a sixth active region arranged in a sequence from left to right on the substrate, wherein the first active region, the second active region, the third active region, the fourth active region, the fifth active region and the sixth active region are parallel to each other; a seventh active region contacting the third active region and the fifth active region, wherein the seventh active region is perpendicular to the fifth active region; an eighth active region contacting the fourth active region and the sixth active region, wherein the eighth active region is perpendicular to the sixth active region; a first gate line covering the first active region, the second active region and the fourth active region; a second gate line covering the fourth active region, wherein the second gate line is parallel to the first gate line; a third gate line covering the first active region, the second active region and the third active region; a fourth gate line covering the third active region, wherein the fourth gate line is parallel to the third gate line; a first metal line electrically connecting to the first gate line and the second gate line, wherein the first metal line is perpendicular to the eighth active region; and a second metal line electrically connecting to the third gate line and the fourth gate line, wherein the second metal line is perpendicular to the seventh active region.

11. The SRAM structure of claim 10 , wherein the first active region, the second active region, the third active region and the fourth active region do not connect to each other structurally.

12. The SRAM structure of claim 10 , further comprising: a third gate line and a sixth gate line covering the fifth active region, wherein the third gate line and the sixth gate line are perpendicular to the fifth active region; and a seventh gate line and an eighth gate line covering the sixth active region, wherein the seventh gate line and the eighth gate line are perpendicular to the sixth active region.

13. The SRAM structure of claim 12 , wherein: a first pull down transistor and a second pull down transistor are disposed in the third active region; a third pull down transistor and a fourth pull down transistor are disposed in the fourth active region; a first pull up transistor is disposed in the first active region; and a second pull up transistor is disposed in the second active region.

14. The SRAM structure of claim 13 , wherein: a first passing gate transistor and a second passing gate transistor are disposed in the sixth active region; and a third passing gate transistor and a fourth passing gate transistor are disposed in the fifth active region.

15. The SRAM structure of claim 14 , wherein the first pull up transistor, the second pull up transistor, the first pull down transistor, the second pull down transistor, the third pull down transistor and the fourth pull down transistor form two cross-coupled inverters.

16. The SRAM structure of claim 15 , wherein the first passing gate transistor and the third passing gate transistor serve as a first terminal of the two cross-coupled inverters, and the second passing gate transistor and the fourth gate transistor serve as a second terminal of the two cross-coupled inverters.

17. The SRAM structure of claim 10 , wherein part of the first metal line overlaps the eighth active region and part of the second metal line overlaps the seventh active region.