A processing apparatus supporting register renaming is provided with checkpoint circuitry to capture register mapping checkpoints indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution, and register group tracking circuitry to maintain tracking information for groups of logical registers. The tracking information for a given group indicates whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last checkpoint was captured. When capturing a new register mapping checkpoint, unchanged groups of logical registers are excluded from the new register mapping checkpoint. This can save power in a register mapping checkpointing scheme.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: processing circuitry to perform data processing in response to micro-operations; register renaming circuitry to map logical registers specified by the micro-operations to physical registers provided in hardware; checkpoint circuitry to capture register mapping checkpoints, each register mapping checkpoint indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution; and register group tracking circuitry to maintain tracking information for a plurality of groups of logical registers, each group comprising one or more logical registers, the tracking information for a given group indicating whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last register mapping checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last register mapping checkpoint was captured; in which: when capturing a new register mapping checkpoint, the checkpoint circuitry is configured to exclude from the new register mapping checkpoint the speculative register mappings for logical registers in an unchanged group of logical registers; and when capturing a new register mapping checkpoint, the checkpoint circuitry is configured to suppress clocking of a subset of checkpoint storage elements for storing checkpointed speculative register mappings for the unchanged group of logical registers.
2. The apparatus according to claim 1 , in which each group comprises a plurality of logical registers.
3. The apparatus according to claim 1 , in which when the checkpoint circuitry captures the new register mapping checkpoint, the register group tracking circuitry is configured to reset the tracking information to indicate that all groups of logical registers are unchanged groups of logical registers.
4. The apparatus according to claim 1 , in which when capturing the new register mapping checkpoint, the checkpoint circuitry is configured to record checkpoint state information associated with the new register mapping checkpoint, the checkpoint state information indicative of which groups of logical registers have their speculative register mappings included in the new register mapping checkpoint.
5. The apparatus according to claim 1 , comprising a speculative rename table to record current speculative register mappings between logical registers and physical registers; in which: in response to a misprediction detected for a mispredict point of execution, the checkpoint circuitry is configured to restore, to the speculative rename table, speculative register mappings selected from at least one pre-misprediction register mapping checkpoint corresponding to an older point of execution than the mispredict point.
6. The apparatus according to claim 5 , in which the checkpoint circuitry is capable of restoring, to the speculative rename table, speculative register mappings combined from a plurality of different register mapping checkpoints.
7. The apparatus according to claim 5 , in which in response to the misprediction, the checkpoint circuitry is configured to determine, separately for each group of logical registers, which of the plurality of register mapping checkpoints is a youngest pre-misprediction register mapping checkpoint which includes speculative register mappings for that group of logical registers and corresponds to an older point of execution than the mispredict point; and for each group of logical registers, the checkpoint circuitry is configured to restore, to the speculative rename table, the speculative register mappings specified for that group of logical registers by the youngest pre-misprediction register mapping checkpoint determined for that group of logical registers.
8. The apparatus according to claim 5 , comprising a register commit queue to record a sequence of updates to speculative register mappings; in which: following restoration of speculative register mappings to the speculative rename table based on speculative register mappings corresponding to a restore point of execution earlier than the mispredict point of execution, the checkpoint circuitry is configured to apply further updates to the speculative rename table based on one or more speculative register mappings recorded in the register commit queue which correspond to points of execution between the restore point of execution and the mispredict point of execution.
9. The apparatus according to claim 1 , in which in response to a misprediction detected for a mispredict point of execution, the checkpoint circuitry is configured to flush a post-misprediction register mapping checkpoint corresponding to a younger point of execution than the mispredict point of execution.
10. The apparatus according to claim 9 , in which each register mapping checkpoint is associated with checkpoint state information indicative of which groups of logical registers have their speculative register mappings included in that register mapping checkpoint; and when at least one register mapping checkpoint is flushed in response to the misprediction, the register group tracking circuitry is configured to update the tracking information based on the checkpoint state information associated with an oldest post-misprediction register mapping checkpoint.
11. The apparatus according to claim 10 , in which the register group tracking circuitry is configured to update the tracking information to indicate as the changed group of logical registers a group of logical registers indicated by the checkpoint state information as being included in said oldest post-misprediction register mapping checkpoint, and to indicate as the unchanged group of logical registers a group of logical registers indicated by the checkpoint state information as being excluded from said oldest post-misprediction register mapping checkpoint.
12. The apparatus according to claim 9 , in which in response to the misprediction when no register mapping checkpoints have been captured since the mispredict point of execution, the register group tracking circuitry is configured to retain a current value of the tracking information, so that when execution resumes after handling of the misprediction, the tracking information is the same as the tracking information which was updated based on a mispredicted flow of execution prior to the misprediction being detected.
13. The apparatus according to claim 1 , in which in response to a micro-operation specifying a destination logical register, the register group tracking circuitry is configured to set the tracking information to indicate that a group of logical registers including the destination logical register is said changed group of logical registers.
14. An apparatus comprising: processing circuitry to perform data processing in response to micro-operations; register renaming circuitry to map logical registers specified by the micro-operations to physical registers provided in hardware; checkpoint circuitry to capture register mapping checkpoints, each register mapping checkpoint indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution; register group tracking circuitry to maintain tracking information for a plurality of groups of logical registers, each group comprising one or more logical registers, the tracking information for a given group indicating whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last register mapping checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last register mapping checkpoint was captured; a speculative rename table to record current speculative register mappings between logical registers and physical registers; and an architectural rename table to record non-speculative register mappings between logical registers and physical registers corresponding to a commit point of execution; in which: when capturing a new register mapping checkpoint, the checkpoint circuitry is configured to exclude from the new register mapping checkpoint the speculative register mappings for logical registers in an unchanged group of logical registers; in response to a misprediction detected for a mispredict point of execution, the checkpoint circuitry is configured to restore, to the speculative rename table, speculative register mappings selected from at least one pre-misprediction register mapping checkpoint corresponding to an older point of execution than the mispredict point; and when, for a given group of logical registers, the checkpoint circuitry identifies that none of the captured register mapping checkpoints which correspond to an older point of execution than the mispredict point includes speculative register mappings for the given group of logical registers, the checkpoint circuitry is configured to restore to the speculative rename table the non-speculative register mappings specified by the architectural rename table for said given group of logical registers.
15. A data processing method comprising: performing data processing in response to micro-operations; mapping logical registers specified by the micro-operations to physical registers provided in hardware; capturing register mapping checkpoints, each register mapping checkpoint indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution; and maintaining tracking information for a plurality of groups of logical registers, each group comprising one or more logical registers, the tracking information for a given group indicating whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last register mapping checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last register mapping checkpoint was captured; in which: when a new register mapping checkpoint is captured, speculative register mappings for logical registers in an unchanged group of logical registers are excluded from the new register mapping checkpoint; and the method comprises: when capturing a new register mapping checkpoint, suppressing clocking of a subset of checkpoint storage elements for storing checkpointed speculative register mappings for the unchanged group of logical registers.
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June 19, 2019
April 13, 2021
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