GOA circuit and display panel

1. A gate driver on array (GOA) circuit, comprising N stage GOA units, and an n-th stage GOA unit comprises a forward scan control module, a reverse scan control module, a pull-up module, a pull-down module, and a function module, wherein 2<n<N−1, and n and N are positive integers; the forward scan control module is connected to a forward signal, an (n+1)th stage clock signal and an (n−2)th stage scan signal, and is electrically connected to a first node and a second node; the forward scan control module is configured to raise a potential of the first node and control a potential of the second node according to the forward signal, the (n+1)th stage clock signal, and the (n−2)th stage scan signal; the reverse scan control module is connected to a reverse signal, an (n−1)th stage clock signal and an (n+2)th stage scan signal, and is electrically connected to the first node and the second node; the reverse scan control module is configured to raise the potential of the first node and control the potential of the second node according to the reverse signal, the (n−1)th stage clock signal, and the (n+2)th stage scan signal; the pull-up module is connected to a constant-voltage low-level signal, a constant-voltage high-level signal, and an n-th stage clock signal, and is electrically connected to the first node and a scan signal output end; the pull-up module is configured to control a potential of the scan signal output end according to the constant-voltage low-level signal, the constant-voltage high-level signal, the n-th clock signal, and the potential of the first node; the pull-down module is connected to the constant-voltage high-level signal and the constant-voltage low-level signal, and is electrically connected to the first node, the second node, and the scan signal output end; the pull-down module is configured to pull down the potential of the first node and the potential of the scan signal output end according to the constant-voltage high-level signal, the constant-voltage low-level signal, and the potential of the second section; and the function module is connected to a first function control signal, a second function control signal, a third function control signal, and a fourth function control signal, and is electrically connected to the pull-down module and the scan signal output end; the function module is configured to control the potential of the first node and the potential of the scan signal output end according to the first function control signal, the second function control signal, the third function control signal and the fourth function control signal.

2. The GOA circuit of claim 1 , wherein the forward scan control module comprises a first transistor and a third transistor; a gate of the first transistor is electrically connected to the (n−2)th scan signal, and a source of the first transistor is electrically connected to the forward scan signal and a gate of the third transistor, a drain of the first transistor is electrically connected to the first node, a source of the third transistor is electrically connected to the (n+1)th stage clock signal, and a drain of the third transistor is electrically connected to the second node.

3. The GOA circuit of claim 1 , wherein the reverse scan control module comprises a second transistor and a fourth transistor; a gate of the second transistor is electrically connected to the (n+2)th scan signal, and a source of the second transistor is electrically connected to the reverse scan signal and a gate of the fourth transistor, a drain of the second transistor is electrically connected to the first node, a source of the fourth transistor is electrically connected to the (n−1)th stage clock signal, and a drain of the fourth transistor is electrically connected to the second node.

4. The GOA circuit of claim 1 , wherein the pull-up module comprises a seventh transistor, a ninth transistor, and a first capacitor; a gate of the seventh transistor is electrically connected to the constant-voltage high-level signal, a source of the seventh transistor is electrically connected to the first node, and a drain of the seventh transistor is electrically connected to a gate of the ninth transistor, the gate of the ninth transistor is electrically connected to the n-th clock signal, and the gate of the ninth transistor is electrically connected to the scan signal output end; one end of the first capacitor is electrically connected to the first node, and another end of the first capacitor is electrically connected to the constant-voltage low-level signal.

5. The GOA circuit of claim 1 , wherein the pull-down module comprises a fifth transistor, a sixth transistor, an eighth transistor, a tenth transistor, and a second capacitor; a gate of the fifth transistor, a drain of the sixth transistor, a drain of the eighth transistor, a gate of the tenth transistor, and one end of the second capacitor are all electrically connected to a third node; a source of the fifth transistor, a source of the sixth transistor, a source of the tenth transistor, and another end of the second capacitor are all electrically connected to the constant-voltage low-level signal; a drain of the fifth transistor and a gate of the sixth transistor are both electrically connected to the first node; a gate of the eighth transistor is electrically connected to the second node, a source of the eight transistors is electrically connected to the constant-voltage high-level signal, and a drain of the tenth transistor is electrically connected to the scan signal output end.

6. The GOA circuit of claim 5 , wherein the functional module comprises an eleventh transistor and a twelfth transistor; a gate of the eleventh transistor is electrically connected to the first function control signal, a source of the eleventh transistor is electrically connected to the third function control signal, and a drain of the eleventh transistor is electrically connected to the third node; and a gate of the twelfth transistor is electrically connected to the second function control signal, a source of the twelfth transistor is electrically connected to the fourth function control signal, and a drain of the twelfth transistor is electrically connected to the scan signal output end.

7. The GOA circuit of claim 6 , wherein the GOA circuit has a reset mode, an abnormal power-off mode, and a full shutdown mode; when the GOA circuit is in the reset mode, the first function control signal and the third function control signal are at a high potential; when the GOA circuit is in the abnormal power-off mode, the first function control signal, the second function control signal, and the fourth function control signal are all at the high potential, and the third function control signal is at a low potential; and when the GOA circuit is in the full-off mode, the second function control signal is at the high potential, and the fourth function control signal is at the low potential.

8. The GOA circuit of claim 1 , wherein the GOA circuit accesses a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; and the (4k+1)th stage clock signal and the first clock signal are the same signal, the (4k+2)th stage clock signal and the second clock signal are the same signal, the (4k+3)th stage clock signal and the third clock signal are the same signal, the (4k+4)th stage clock signal and the fourth clock signal are the same signal, wherein k is greater than or equal to 0, and k is an integer.

9. The GOA circuit of claim 1 , wherein the GOA circuit accesses a first start signal and a second start signal; when the GOA circuit is in the forward scanning mode, the first-stage GOA unit accesses the first start signal, and the second-stage GOA unit accesses the second start signal; and when the GOA circuit is in the reverse scan mode, the GOA unit of an Nth stage accesses the first start signal, and the GOA unit of the (N−1)th stage accesses the second start signal.

10. A display panel, comprising a GOA circuit, the GOA circuit comprises N stage GOA units, and a n-th stage GOA unit comprises a forward scan control module, a reverse scan control module, a pull-up module, a pull-down module, and a function module, wherein 2<n<N−1, and n and N are positive integers; the forward scan control module is connected to a forward signal, an (n+1)th stage clock signal and an (n−2)th stage scan signal, and is electrically connected to a first node and a second node; the forward scan control module is configured to raise a potential of the first node and control a potential of the second node according to the forward signal, the (n+1)th stage clock signal, and the (n−2)th stage scan signal; the reverse scan control module is connected to a reverse signal, an (n−1)th stage clock signal and an (n+2)th stage scan signal, and is electrically connected to the first node and the second node; the reverse scan control module is configured to raise the potential of the first node and control the potential of the second node according to the reverse signal, the (n−1)th stage clock signal, and the (n+2)th stage scan signa; the pull-up module is connected to a constant-voltage low-level signal, a constant-voltage high-level signal, and an n-th stage clock signal, and is electrically connected to the first node and a scan signal output end; the pull-up module is configured to control a potential of the scan signal output end according to the constant-voltage low-level signal, the constant-voltage high-level signal, the n-th clock signal, and the potential of the first node; the pull-down module is connected to the constant-voltage high-level signal and the constant-voltage low-level signal, and is electrically connected to the first node, the second node, and the scan signal output end; the pull-down module is configured to pull down the potential of the first node and the potential of the scan signal output end according to the constant-voltage high-level signal, the constant-voltage low-level signal, and the potential of the second section; and the function module is connected to a first function control signal, a second function control signal, a third function control signal, and a fourth function control signal, and is electrically connected to the pull-down module and the scan signal output end; the function module is configured to control the potential of the first node and the potential of the scan signal output end according to the first function control signal, the second function control signal, the third function control signal and the fourth function control signal.

11. The display panel of claim 10 , wherein the forward scan control module comprises a first transistor and a third transistor; a gate of the first transistor is electrically connected to the (n−2)th scan signal, and a source of the first transistor is electrically connected to the forward scan signal and a gate of the third transistor, a drain of the first transistor is electrically connected to the first node, a source of the third transistor is electrically connected to the (n+1)th stage clock signal, and a drain of the third transistor is electrically connected to the second node.

12. The display panel of claim 10 , wherein the reverse scan control module comprises a second transistor and a fourth transistor; a gate of the second transistor is electrically connected to the (n+2)th scan signal, and a source of the second transistor is electrically connected to the reverse scan signal and a gate of the fourth transistor, a drain of the second transistor is electrically connected to the first node, a source of the fourth transistor is electrically connected to the (n−1)th stage clock signal, and a drain of the fourth transistor is electrically connected to the second node.

13. The display panel of claim 10 , wherein the pull-up module comprises a seventh transistor, a ninth transistor, and a first capacitor; a gate of the seventh transistor is electrically connected to the constant-voltage high-level signal, a source of the seventh transistor is electrically connected to the first node, and a drain of the seventh transistor is electrically connected to a gate of the ninth transistor, the gate of the ninth transistor is electrically connected to the n-th clock signal, and the gate of the ninth transistor is electrically connected to the scan signal output end; one end of the first capacitor is electrically connected to the first node, and another end of the first capacitor is electrically connected to the constant-voltage low-level signal.

14. The display panel of claim 10 , wherein the pull-down module comprises a fifth transistor, a sixth transistor, an eighth transistor, a tenth transistor, and a second capacitor; a gate of the fifth transistor, a drain of the sixth transistor, a drain of the eighth transistor, a gate of the tenth transistor, and one end of the second capacitor are all electrically connected to a third node; a source of the fifth transistor, a source of the sixth transistor, a source of the tenth transistor, and another end of the second capacitor are all electrically connected to the constant-voltage low-level signal; a drain of the fifth transistor and a gate of the sixth transistor are both electrically connected to the first node; a gate of the eighth transistor is electrically connected to the second node, a source of the eight transistors is electrically connected to the constant-voltage high-level signal, and a drain of the tenth transistor is electrically connected to the scan signal output end.

15. The display panel of claim 14 , wherein the functional module comprises an eleventh transistor and a twelfth transistor; a gate of the eleventh transistor is electrically connected to the first function control signal, a source of the eleventh transistor is electrically connected to the third function control signal, and a drain of the eleventh transistor is electrically connected to the third node; and a gate of the twelfth transistor is electrically connected to the second function control signal, a source of the twelfth transistor is electrically connected to the fourth function control signal, and a drain of the twelfth transistor is electrically connected to the scan signal output end.

16. The display panel of claim 15 , wherein the GOA circuit has a reset mode, an abnormal power-off mode, and a full shutdown mode; when the GOA circuit is in the reset mode, the first function control signal and the third function control signal are at a high potential; when the GOA circuit is in the abnormal power-off mode, the first function control signal, the second function control signal, and the fourth function control signal are all at the high potential, and the third function control signal is at a low potential; and when the GOA circuit is in the full-off mode, the second function control signal is at the high potential, and the fourth function control signal is at the low potential.

17. The display panel of claim 10 , wherein the GOA circuit accesses a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; and the (4k+1)th stage clock signal and the first clock signal are the same signal, the (4k+2)th stage clock signal and the second clock signal are the same signal, the (4k+3)th stage clock signal and the third clock signal are the same signal, the (4k+4)th stage clock signal and the fourth clock signal are the same signal, wherein k is greater than or equal to 0, and k is an integer.

18. The display panel of claim 10 , wherein the GOA circuit accesses a first start signal and a second start signal; when the GOA circuit is in the forward scanning mode, the first-stage GOA unit accesses the first start signal, and the second-stage GOA unit accesses the second start signal; and when the GOA circuit is in the reverse scan mode, the GOA unit of an Nth stage accesses the first start signal, and the GOA unit of the (N−1)th stage accesses the second start signal.