A method for memory modification resulting in a test probe for examining a program under test substantially during run-time is provided. The ability to inject faults or errors in order to test a reaction of the program to a fault in a particular state and to individually replace access to a regular operand by accessing a shadow operand allow for non-intrusive tests while the program is substantially executed in real-time. The program itself is not substantially altered for testing purposes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manipulating a program during execution for testing of the program in a computer during run-time, providing the program comprising compiling, linking, or compiling and linking first program code of the program to be tested with second program code including routines for allocating a delimited memory structure, providing for registers or other memory cells under the control of the second program code, and providing extended instructions for accessing or administering a shadow variable instead of a variable, the program being stored and comprising instructions to be executed by a processor of the computer, the method comprising: allocating a first memory structure for storing at least one operand of the program, each operand stored in a first memory cell by an associated first address in the first memory structure; allocating a second memory structure for storing at least one shadow operand that is a modified data value, such that a modified nature compared to an original operand is expressed, each shadow operand stored in a second memory cell by an associated second address in the second memory structure; loading one of the instructions for accessing a first memory cell by an associated first address; querying data instructive of reading or writing a shadow operand on occurrence of a regular instruction for accessing the first memory cell by the first address; and responsive to a positive querying of the data, using an associated second address for accessing a second memory cell of one of the second memory cells instead of the first memory cell.
2. The method of claim 1 , wherein the second memory structure is allocated in a register memory included in the processor or administered by the processor.
3. The method of claim 1 , wherein the second memory structure is allocated in a main memory administered by the processor.
4. The method of claim 1 , wherein the second memory structure includes at least one memory cell for storing a modification indicator, the modification indicator indicating a presence or absence of at least one first address in the second memory structure.
5. The method of claim 4 , wherein the querying of data instructive of reading or writing a shadow operand includes querying the modification indicator.
6. The method of claim 4 , wherein the instructions include an instruction for reading, amending, or reading and amending the modification indicator.
7. The method of claim 1 , wherein the second memory structure includes at least one memory cell for storing a first address of one or more operands of the at least one operand, for each of which a respective shadow operand is present.
8. The method of claim 1 , wherein the second memory structure includes at least one memory cell for storing one or more shadow operands of the at least one shadow operand.
9. The method of claim 1 , wherein the querying of data instructive of reading or writing a shadow operand includes an instruction for replacing an access of the operand by an access of the shadow operand.
10. The method of claim 1 , wherein the querying of data instructive of reading or writing a shadow operand includes querying a presence of the first address in the second memory structure.
11. The method of claim 1 , wherein the processor comprises components for carrying out the method.
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July 31, 2018
May 4, 2021
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