Semiconductor device

1. A semiconductor device, comprising: a first semiconductor structure including a substrate, circuit devices disposed on the substrate, and first bonding pads disposed on the circuit devices; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including, a base layer having a first surface facing the first semiconductor structure and a second surface opposing the first surface; a first memory cell structure including first gate electrodes spaced apart from each other and stacked in a direction perpendicular to the first surface of the base layer, and first channels penetrating through at least portions of the first gate electrodes; a second memory cell structure including second gate electrodes spaced apart from each other and stacked in the direction perpendicular to the first surface, and second channels penetrating through at least portions of the second gate electrodes; bit lines disposed between the first memory cell structure and the second memory cell structure, and electrically connected to the first and second channels in common; first and second conductive layers spaced apart from each other and disposed on the second surface of the base layer; a pad insulating layer disposed on the first and second conductive layers and having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

2. The semiconductor device of claim 1 , further comprising: a connection pad disposed in parallel to the bit lines and electrically connected to the second conductive layer.

3. The semiconductor device of claim 2 , further comprising: a first contact plug disposed between the second conductive layer and the connection pad and electrically connecting the second conductive layer and the connection pad.

4. The semiconductor device of claim 3 , wherein the first contact plug includes a plurality of contact plugs, and the plurality of contact plugs are connected to the second conductive layer.

5. The semiconductor device of claim 3 , wherein the first contact plug is directly connected to the second conductive layer by penetrating through the base layer.

6. The semiconductor device of claim 2 , further comprising: a second contact plug disposed between the connection pad and the second bonding pads and electrically connecting at least one of the second bonding pads to the connection pad.

7. The semiconductor device of claim 2 , wherein the connection pad has a thickness substantially the same as a thickness of the bit lines.

8. The semiconductor device of claim 1 , wherein the first conductive layer overlaps the first and second gate electrodes, and the second conductive layer is spaced apart from the first and second gate electrodes in a horizontal direction so as not to overlap the first and second gate electrodes.

9. The semiconductor device of claim 1 , wherein the first conductive layer is included in a source line applying an electrical signal to the first channels, and the second conductive layer is electrically isolated from the first conductive layer.

10. The semiconductor device of claim 1 , wherein the first and second conductive layers are disposed on substantially the same level and have substantially the same thickness.

11. The semiconductor device of claim 1 , wherein side surfaces of the pad insulating layer defining the opening and an upper surface of the second conductive layer exposed by the opening are exposed externally of the semiconductor device.

12. The semiconductor device of claim 1 , wherein the first and second channels have inclined side surfaces such that widths of the first and second channels decrease in a direction towards the base layer.

13. The semiconductor device of claim 1 , further comprising: a third conductive layer disposed in a lower portion of the second memory cell structure and included in a source line applying an electrical signal to the second channels.

14. A semiconductor device, comprising: a first semiconductor structure including a substrate, circuit devices disposed on the substrate, and first bonding pads disposed on the circuit devices; and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, the second semiconductor structure including, a base layer; memory cell structures stacked in a direction perpendicular to a lower surface of the base layer; at least one wiring line disposed between the memory cell structures and shared between the memory cell structures disposed upwardly and downwardly; first and second conductive layers spaced apart from each other and disposed on an upper surface of the base layer; a pad insulating layer disposed on the first and second conductive layers and having an opening exposing a portion of the second conductive layer; a connection pad disposed in parallel to the at least one wiring line in a lower portion of the second conductive layer and electrically connected to the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in lower portions of the memory cell structures.

15. The semiconductor device of claim 14 , further comprising: contact plugs disposed on an upper surface and a lower surface of the connection pad.

16. The semiconductor device of claim 15 , wherein the second conductive layer is electrically connected to at least one of the second bonding pads through the connection pad and the contact plugs.

17. The semiconductor device of claim 14 , wherein the memory cell structures each include gate electrodes spaced apart from each other and stacked in a direction perpendicular to the lower surface of the base layer, and channels penetrating through the gate electrodes, and the at least one wiring line includes bit lines electrically connected to the channels of the memory cell structures in common.

18. The semiconductor device of claim 17 , wherein the at least one wiring line further includes a source line electrically connected to the channels of the memory cell structures in common.

19. A semiconductor device, comprising: a first semiconductor structure including a substrate, circuit devices disposed on the substrate, and first bonding pads disposed on the circuit devices; and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, the second semiconductor structure including, a base layer; memory cell structures stacked in a direction perpendicular to a lower surface of the base layer on the lower surface, and including gate electrodes stacked vertically; at least one wiring line disposed between the memory cell structures and shared between the memory cell structures disposed upwardly and downwardly; a first conductive layer disposed on the base layer in upper portions of the gate electrodes; a second conductive layer spaced apart from the first conductive layer in a horizontal direction and provided for electrical connection with an external device; a pad insulating layer disposed on the first and second conductive layers and having an opening exposing a portion of the second conductive layer; a connection pad disposed in parallel to the at least one wiring line in a lower portion of the second conductive layer and electrically connected to the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in lower portions of the memory cell structures.

20. The semiconductor device of claim 19 , wherein the first conductive layer is a source line applying an electrical signal to the memory cell structures.