Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a semiconductor substrate; an interconnect structure disposed over the semiconductor substrate, and including a plurality of dielectric layers and a plurality of metal layers stacked over one another in alternating fashion, wherein the plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer; a bottom electrode disposed over and in electrical contact with the lower metal layer; a barrier layer disposed over an upper surface of the bottom electrode; a top electrode disposed over an upper surface of the barrier layer, wherein the top electrode has an electrode top surface in direct electrical contact with a bottom surface of the upper metal layer; a sidewall spacer surrounding an outer periphery of the top electrode, wherein the sidewall spacer has a spacer top surface; an etch stop layer disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer; and wherein an upper surface of the etch stop layer that extends beyond the outer periphery of the spacer top surface angles slightly down toward the lower metal layer.
2. The integrated circuit of claim 1 , wherein the bottom surface of the upper metal layer is in contact with the top spacer surface.
3. The integrated circuit of claim 1 , wherein a width of the bottom surface of the upper metal layer is less than a width of the spacer top surface.
4. The integrated circuit of claim 1 , wherein the barrier layer has sidewalls that are angled at an angle of other than 90-degrees as measured relative to a normal line passing through the upper surface of the bottom electrode.
5. The integrated circuit of claim 1 , wherein the upper metal layer contacts less than an entirety of the electrode top surface.
6. The integrated circuit of claim 1 , wherein the etch stop layer comprises silicon nitride (Si 3 N 4 ).
7. An integrated circuit, comprising: a semiconductor substrate; an interconnect structure disposed over the semiconductor substrate, and including a plurality of metal layers stacked over one another and disposed in a dielectric structure, wherein the plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer; a bottom electrode disposed over and in electrical contact with the lower metal layer; a barrier layer disposed over an upper surface of the bottom electrode; a top electrode disposed over an upper surface of the barrier layer; a sidewall spacer surrounding an outer periphery of the top electrode, wherein the sidewall spacer has a spacer top surface; and an etch stop layer disposed on top of an outer periphery of the spacer top surface; and wherein an upper surface of the etch stop layer that extends beyond the outer periphery of the spacer top surface angles downward toward the lower metal layer.
8. The integrated circuit of claim 7 , wherein the upper metal layer extends downward along an inner sidewall of the etch stop layer such that a lower surface of the upper metal layer contacts an upper surface of the top electrode.
9. The integrated circuit of claim 8 , wherein the lower surface of the upper metal layer is in contact with the spacer top surface.
10. The integrated circuit of claim 8 , wherein a width of the lower surface of the upper metal layer is less than a width of the spacer top surface.
11. The integrated circuit of claim 7 , wherein the barrier layer has sidewalls that are angled at an angle of other than 90-degrees as measured relative to a normal line passing through an upper surface of the bottom electrode.
12. The integrated circuit of claim 7 , wherein the etch stop layer comprises silicon nitride (Si 3 N 4 ).
13. The integrated circuit of claim 7 , further comprising: a lower etch stop layer disposed over the lower metal layer and beneath the bottom electrode, wherein the bottom electrode extends through the lower etch stop layer to contact the lower metal layer.
14. A memory cell, comprising: a top electrode disposed over an upper surface of a magnetic tunneling junction (MTJ), wherein the top electrode has a top electrode upper surface; a sidewall spacer disposed over an outer periphery of the top electrode, wherein the sidewall spacer has an upper surface; an upper etch stop layer disposed over an outer region of the upper surface of the sidewall spacer, wherein an upper surface of the upper etch stop layer extends beyond the outer region of the upper surface of the sidewall spacer and angles downwardly; and an upper metal line disposed over the top electrode and extending through an opening in the upper etch stop layer such that the upper metal line makes direct physical and electrical contact with the top electrode upper surface.
15. The memory cell of claim 14 , wherein the upper etch stop layer comprises silicon nitride (Si 3 N 4 ).
16. The memory cell of claim 14 , wherein a width of the upper surface of the sidewall spacer combined with a width of the top electrode upper surface is greater than approximately 154 nanometers.
17. The memory cell of claim 14 , further comprising: a lower metal line disposed beneath the top electrode; a lower etch stop layer disposed over the lower metal line and beneath the top electrode, wherein the lower etch stop layer includes an opening over the lower metal line; and a lower electrode disposed beneath the top electrode and over the lower etch stop layer, wherein the lower electrode extends through the opening in the lower etch stop layer to contact the lower metal line.
18. The memory cell of claim 17 , wherein at least one of the upper etch stop layer and the lower etch stop layer comprise silicon and at least one of nitrogen or carbon.
19. The memory cell of claim 14 , wherein the sidewall spacer comprises silicon carbide (SiC).
20. The memory cell of claim 14 , wherein the upper metal line contacts less than an entirety of the top electrode upper surface, and wherein the upper metal line is disposed on top of an inner region of the upper surface of the sidewall spacer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 12, 2019
May 11, 2021
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