Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device comprising: a memory array comprising a plurality of memory elements arranged in a plurality of slices; a word line driver coupled to the memory array; and an access signal generator coupled to the word line driver, the access signal generator comprising a controller to cause the word line driver to sequentially apply an access signal to the plurality of slices to access a corresponding slice, wherein a magnitude of the access signal is based at least in part on a position of the corresponding slice in the memory array.
2. The memory device of claim 1 , wherein each of the plurality of slices represents a group of the plurality of memory elements formed by at least one bit line of the memory array.
3. The memory device of claim 1 , wherein the controller is to cause the word line driver to apply the access signal with a first modified magnitude to a first slice of the plurality of slices during a first interval of time and to apply the access signal with a second modified magnitude to a second slice of the plurality of slices during a second interval of time.
4. The memory device of claim 1 , wherein the magnitude of the access signal increases as the distance between the word line driver and the corresponding slice increases.
5. The memory device of claim 1 , further comprising: a second memory array coupled to the word line driver, the second memory array comprising a second plurality of memory elements arranged in a second plurality of slices.
6. The memory device of claim 5 , wherein the controller is to cause the word line driver to apply the access signal with a same magnitude to a slice of the plurality of slices and a slice of the second plurality of slices during different intervals of time.
7. The memory device of claim 5 , wherein the controller is to cause the word line driver to apply the access signal with a same magnitude to a slice of the plurality of slices and a slice of the second plurality of slices during a same interval of time.
8. The memory device of claim 7 , wherein the slice of the plurality of slices and the slice of the second plurality of slices are substantially equidistant from the word line driver.
9. An apparatus comprising: a substrate; a memory array formed above the substrate, the memory array comprising a plurality of memory elements arranged in a plurality of slices; and a word line driver formed on the substrate; and an access signal generator formed on the substrate, the access signal generator comprising a controller to cause the word line driver to sequentially apply an access signal to the plurality of slices to access a corresponding slice, wherein a magnitude of the access signal is based at least in part on a position of the corresponding slice in the memory array.
10. The apparatus of claim 9 , wherein each of the plurality of slices represents a group of the plurality of memory elements formed by at least one bit line of the memory array.
11. The apparatus of claim 9 , wherein the controller is to cause the word line driver to apply the access signal with a first modified magnitude to a first slice of the plurality of slices during a first interval of time and to apply the access signal with a second modified magnitude to a second slice of the plurality of slices during a second interval of time.
12. The apparatus of claim 9 , wherein the magnitude of the access signal increases as the distance between the word line driver and the corresponding slice increases.
13. The apparatus of claim 9 , further comprising: a second memory array coupled to the word line driver, the second memory array comprising a second plurality of memory elements arranged in a second plurality of slices.
14. The apparatus of claim 13 , wherein the controller is to cause the word line driver to apply the access signal with a same magnitude to a slice of the plurality of slices and a slice of the second plurality of slices during different intervals of time.
15. The apparatus of claim 13 , wherein the controller is to cause the word line driver to apply the access signal with a same magnitude to a slice of the plurality of slices and a slice of the second plurality of slices during a same interval of time.
16. The apparatus of claim 15 , wherein the slice of the plurality of slices and the slice of the second plurality of slices are substantially equidistant from the word line driver.
17. An integrated circuit comprising: a logic layer formed on a substrate, the logic layer comprising an access signal generator; a word line driver formed on the substrate; and a memory comprising one or more layers formed above the substrate, the memory comprising an array comprising a plurality of memory elements arranged in a plurality of slices, wherein the access signal generator comprising a controller to cause the word line driver to sequentially apply an access signal to the plurality of slices to access a corresponding slice, wherein a magnitude of the access signal is based at least in part on a position of the corresponding slice in the memory array.
18. The integrated circuit of claim 17 , wherein each of the plurality of slices represents a group of the plurality of memory elements formed by at least one bit line of the memory array.
19. The integrated circuit of claim 17 , wherein the controller is to cause the word line driver to apply the access signal with a first modified magnitude to a first slice of the plurality of slices during a first interval of time and to apply the access signal with a second modified magnitude to a second slice of the plurality of slices during a second interval of time.
20. The integrated circuit of claim 17 , wherein the magnitude of the access signal increases as the distance between the word line driver and the corresponding slice increases.
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April 2, 2020
May 18, 2021
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