Patentable/Patents/US-11011455
US-11011455

Electronic package structure with improved board level reliability

PublishedMay 18, 2021
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.

Patent Claims
18 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for providing an electronic package structure, comprising: providing an electronic component comprising: a substrate comprising: a die pad having a die pad top surface, an opposing die pad bottom surface, and die pad side surfaces, wherein the die pad comprises a conductive material; leads laterally spaced apart from the die pad and having lead top surfaces, opposing lead bottom surfaces, and lead side surfaces; and a substrate encapsulant interposed between the die pad and the leads, wherein the substrate encapsulant has a substrate encapsulant top surface and an opposing substrate encapsulant bottom surface, wherein the die pad bottom surface and the lead bottom surfaces lie on a first plane and the substrate encapsulant bottom surface lies on a second plane that is different than the first plane, wherein the substrate encapsulant top surface terminates proximate to the lead top surfaces and the die pad top surface so that the lead top surfaces and the die pad top surface are exposed outside of the substrate encapsulant top surface, and wherein the lead side surfaces and the die pad side surfaces are covered by the substrate encapsulant; an electronic device having a first major surface and a second major surface opposite to the first major surface and a pair of opposing outer edges in a cross-sectional view, wherein: the electronic device is connected to the substrate such that the first major surface of the electronic device is attached with conductive bumps to the die pad top surface and the lead top surfaces, and the outer edges overlap an opposing pair of the leads in the cross-sectional view; and providing a package body encapsulating the electronic device and the substrate encapsulant top surface such that the substrate encapsulant bottom surface is exposed outside the package body; providing a circuit board having a circuit pattern formed thereon; and connecting the substrate to the circuit pattern using first conductive structures, wherein: the substrate comprises a first lead having a first lead portion exposed to the outside of the substrate bottom surface and second lead portion laterally extending towards the die pad and having a recessed bottom surface encapsulated by the substrate encapsulant; the electronic device comprises a second conductive structure adjacent to the first major surface; the second conductive structure is connected to the second lead portion at a first connection point with one of the conductive bumps; connecting the substrate to the circuit pattern comprises connecting the first lead to the circuit pattern at a second connection point; the first connection point is laterally separated from the second connection point; and the electronic device overlaps the first connection point but not the second connection point.

2

2. The method of claim 1 , wherein: providing the electronic component comprises: providing the die pad comprising pad portions defined in the die pad bottom surface, wherein the pad portions are separated by recesses; and providing the substrate encapsulant disposed within the recesses.

3

3. The method of claim 1 , wherein: the substrate encapsulant and the package body comprise separate layers; and the die pad comprises a width that is less than that of the electronic device.

4

4. The method of claim 1 , wherein: providing the electronic component comprises providing the die pad bottom surface comprising a continuous and substantially planar surface; and connecting the substrate to the circuit pattern comprises: connecting the die pad bottom surface to a first portion of the circuit pattern with a first conductive structure; and connecting a lead to a second portion of the circuit pattern with a second conductive structure, wherein the first conductive structure has a greater width than the second conductive structure.

5

5. The method of claim 4 , wherein: connecting the die pad bottom surface comprises providing the first conductive structure extending entirely across the die pad bottom surface.

6

6. The method of claim 1 , wherein: connecting the substrate to the circuit pattern comprises: providing a first one of the first conductive structures surrounding vertical side surfaces of the die pad protruding from the substrate bottom surface; and providing a second one of the first conductive structures surrounding vertical side surfaces of one of the leads protruding from the substrate bottom surface.

7

7. The method of claim 1 , wherein: providing the electronic component comprises providing the die pad having a lateral width configured to accommodate more than one conductive bump.

8

8. An electronic package structure comprising: a substrate comprising: a die pad having a die pad top surface and an opposing die pad bottom surface, wherein the die pad comprises a conductive material; leads laterally spaced apart from the die pad each lead having a lead top surface and an opposing lead bottom surface; and a substrate encapsulant interposed between the die pad and the leads, wherein the substrate encapsulant has a substrate top surface and an opposing substrate bottom surface; and an electronic die electrically coupled to the die pad and the leads, wherein: at least one lead comprises: a first lead portion exposed to the outside of the substrate bottom surface and defining a first connection point for attaching the electronic package structure to a next level of assembly; and a second lead portion laterally extending towards the die pad and having a recessed bottom surface encapsulated by the substrate encapsulant, the second lead portion defining a second connection point for attaching to the electronic die, wherein the first connection point is laterally separated from the second connection point, wherein a conductive structure on the electronic die is attached to the second lead portion at the second connection point, and wherein the electronic die overlaps the second connection point but not the first connection point.

9

9. The structure of claim 8 , wherein: the die pad bottom surface comprises a plurality of pad portions being separated by recesses; and the substrate encapsulant is disposed within the recesses.

10

10. The structure of claim 9 , further comprising: conductive bumps disposed on each pad portion of the plurality of pad portions and the lead bottom surfaces.

11

11. The structure of claim 8 , wherein: the leads comprises lead top surfaces and opposing lead bottom surfaces; the die pad bottom surface and the lead bottom surfaces lie on a first plane and the substrate bottom surface lies a on a second plane that is different that the first plane; the die pad comprises a lateral width that is different than that of the one lead; and the structure further comprises conductive bumps disposed on the lead bottom surfaces.

12

12. The structure of claim 8 , further comprising: a package body encapsulating the electronic die and the substrate top surface, wherein: the substrate bottom surface is exposed outside of the package body.

13

13. The structure of claim 8 , further comprising: a package body encapsulating the electronic die and the substrate top surface, wherein: the substrate bottom surface is exposed outside the package body; the electronic die comprises a plurality of conductive structures on a major surface; the plurality of conductive structures are electrically coupled to the leads and the die pad with conductive bumps; and more than one conductive bump connects the electronic die to the die pad.

14

14. A method for providing an electronic package structure, comprising: providing a substrate including: a die pad and leads spaced apart from the die pad, wherein the leads each comprise first portions and second portions integral with the first portions; and a substrate encapsulant interposed between the die pad and the leads, the substrate encapsulant comprising a substrate encapsulant top surface and an opposing substrate encapsulant bottom surface, wherein top surfaces of the leads and a top surface of the die pad are exposed from the substrate encapsulant top surface, and bottom surfaces of the first portions of the leads are exposed from the substrate encapsulant bottom surface; providing an electronic device; connecting the electronic device to the second portions of the leads with conductive bumps to where the top surfaces of the leads are exposed from the substrate encapsulant top surface, wherein: the second portions of the leads extend towards the die pad and have recessed bottom surfaces encapsulated by the substrate encapsulant; the first portions of the leads are configured to define first connection points for attaching the electronic package structure to a next level of assembly; the electronic device is connected to the second portions of the leads with the conductive bumps at second connection points; the first connection points and the second connection points are laterally separated from each other; and the electronic device overlaps the second connection points but not the first connections point; and providing a package body encapsulating the electronic device and substrate encapsulant top surface such that the substrate encapsulant bottom surface is exposed outside of the package body.

15

15. The method of claim 14 , wherein: providing the substrate comprises providing the second portions of the leads angled at less than 90 degrees with respect to the first portions of the leads in a top plan view, where at least one second portion has a larger width than another second portion.

16

16. The method of claim 14 , wherein: providing the substrate encapsulant comprises exposing the die pad and the leads in the substrate bottom surface.

17

17. The method of claim 14 , wherein providing the substrate comprises: providing the substrate encapsulant such that the die pad and the leads protrude outward from the substrate bottom surface to provide the die pad and the leads with exposed side surfaces configured to engage solder structures.

18

18. The method of claim 14 , wherein: the substrate encapsulant and the package body comprise separate material layers; and the die pad comprises a lateral width that can accommodate more than one conductive bump.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

February 10, 2018

Publication Date

May 18, 2021

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “Electronic package structure with improved board level reliability” (US-11011455). https://patentable.app/patents/US-11011455

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.