A semiconductor storage device includes first to third wirings extending in a first direction and adjacent in a second direction intersecting the first direction, fourth to sixth wirings extending in the second direction and adjacent in the first direction, memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings, a circuit configured to output a first voltage, second and third voltages higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage. In a write operation for memory cells connected to the first and fourth wirings, the first, fourth, second, fifth and third voltages are transferred to the first, second, third, fourth, and fifth wirings, respectively, and the third voltage is transferred to the sixth wiring.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor storage device comprising: a control circuit; a first wiring extending in a first direction; a second wiring and a third wiring, each extending in the first direction and being adjacent to the first wiring in a second direction intersecting the first direction; a fourth wiring extending in the second direction; a fifth wiring and a sixth wiring, each extending in the second direction and being adjacent to the fourth wiring in the first direction; a plurality of memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings; a voltage output circuit configured to output a first voltage, a second voltage higher than the first voltage, a third voltage higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage; and a voltage transfer circuit connected to the first to sixth wirings and the voltage output circuit, wherein, at a predetermined timing of a write operation for memory cells connected to the first wiring and the fourth wiring, the control circuit is configured to: transfer the first voltage to the first wiring; transfer the fourth voltage to the second wiring; transfer the second voltage to the third wiring; transfer the fifth voltage to the fourth wiring; transfer the third voltage to the fifth wiring; and transfer the third voltage to the sixth wiring.
2. The semiconductor storage device according to claim 1 , wherein each of the memory cells includes a variable resistance film and a chalcogen film.
3. The semiconductor storage device according to claim 1 , wherein the fourth to sixth wirings are farther from a substrate than the first to third wirings.
4. The semiconductor storage device according to claim 1 , wherein magnitudes of the second voltage and the third voltage match or substantially match each other.
5. The semiconductor storage device according to claim 1 , wherein the plurality of memory cells include: first to third memory cells connected to the fourth wiring; fourth to sixth memory cells connected to the fifth wiring; and seventh to ninth memory cells connected to the sixth wiring, and the semiconductor storage device further comprises: a first insulating film formed on side surfaces of the first to third memory cells in the first direction and extending in the second direction; a second insulating film formed on side surfaces of the fourth to sixth memory cells in the first direction and extending in the second direction; and a third insulating film formed on side surfaces of the seventh to ninth memory cells in the first direction and extending in the second direction.
6. A semiconductor storage device comprising: a control circuit; a first wiring extending in a first direction; a second wiring and a third wiring, each extending in the first direction and being adjacent to the first wiring in a second direction intersecting the first direction; a fourth wiring extending in the second direction; a fifth wiring and a sixth wiring, each extending in the second direction and being adjacent to the fourth wiring in the first direction; a plurality of memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings; a voltage output circuit configured to output a first voltage, a second voltage lower than the first voltage, a third voltage lower than the first voltage, a fourth voltage lower than the second voltage and the third voltage, and a fifth voltage lower than the fourth voltage; and a voltage transfer circuit connected to the first to sixth wirings and the voltage output circuit, wherein, at a predetermined timing of a write operation for memory cells connected to the first wiring and the fourth wiring, the control circuit is configured to: transfer the first voltage to the first wiring; transfer the fourth voltage to the second wiring; transfer the second voltage to the third wiring; transfer the fifth voltage to the fourth wiring; transfer the third voltage to the fifth wiring; and transfer the third voltage to the sixth wiring.
7. The semiconductor storage device according to claim 6 , wherein each of the memory cells includes a variable resistance film and a chalcogen film.
8. The semiconductor storage device according to claim 7 , wherein the fourth to sixth wirings are farther from a substrate than the first to third wirings.
9. The semiconductor storage device according to claim 6 , wherein magnitudes of the second voltage and the third voltage match or substantially match each other.
10. The semiconductor storage device according to claim 6 , wherein the plurality of memory cells include: first to third memory cells connected to the fourth wiring; fourth to sixth memory cells connected to the fifth wiring; and seventh to ninth memory cells connected to the sixth wiring, the semiconductor storage device further comprises: a first insulating film formed on side surfaces of the first to third memory cells in the first direction and extending in the second direction; a second insulating film formed on side surfaces of the fourth to sixth memory cells in the first direction and extending in the second direction; and a third insulating film formed on side surfaces of the seventh to ninth memory cells in the first direction and extending in the second direction.
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March 3, 2020
May 18, 2021
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