Semiconductor structure

1. A semiconductor structure comprising: a plurality of devices, wherein each of the plurality of devices includes a first surface disposed with a conductive structure; and a molding disposed between the plurality of devices, wherein the molding includes a first surface coupled to the first surfaces of the plurality of devices; and a redistribution layer (RDL) on the first surfaces of the plurality of devices and the first surface of the molding, wherein the RDL comprises a first portion directly over the first surface of the molding, a second portion directly over the first surfaces of the plurality of devices, a bottom surface of the first portion is in contact with the first surface of the molding, a bottom surface of the second portion is in contact with the first surfaces of the plurality of devices, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

2. The semiconductor structure of claim 1 , wherein each of the plurality of devices comprises at least an active component disposed within the first surface.

3. The semiconductor structure of claim 1 , wherein the thickness of the first portion of the RDL is substantially greater than the thickness of the second portion of the RDL about 5 μm.

4. The semiconductor structure of claim 1 , wherein the plurality of devices include at least one unpackaged device and at least one packaged device.

5. The semiconductor structure of claim 4 , wherein the unpackaged device includes a die pad contacted with the RDL.

6. The semiconductor structure of claim 1 , wherein the molding comprises a second surface opposite to the first surface of the molding.

7. The semiconductor structure of claim 6 , further comprising a metallic shield disposed in the molding, and two ends of the metallic shield is respectively aligned with the first surface of the molding and the second surface of the molding.

8. The semiconductor structure of claim 6 , further comprising a metallic layer covering the second surface of the molding.

9. The semiconductor structure of claim 1 , wherein the plurality of devices include a bare chip, a ball grid array (BGA) package, a quad flat no leads (QFN) package, a land grid array (LGA) package, a surface mount device (SMD) or a microelectromechanical systems (MEMS) device.

10. A system in package (SiP) comprising: a plurality of devices; a molding disposed between the plurality of devices; a metallic shield disposed within the molding and between two of the plurality of devices; and a redistribution layer (RDL) disposed over the plurality of devices and the molding, wherein the RDL comprises a first portion directly over the molding, a second portion directly over the plurality of the devices, a bottom surface of the first portion is in contact with a surface of the molding, a bottom surface of the second portion is in contact with surfaces of the plurality of devices, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

11. The system in package of claim 10 , wherein the plurality of devices are horizontally arranged and supported by the molding.

12. The system in package of claim 10 , wherein the RDL comprise a plurality of first conductive interconnect structures disposed in the second portion, and the plurality of devices are electrically connected to the first conductive interconnect structure of the RDL.

13. The system in package of claim 12 , wherein the RDL comprise a second conductive interconnect structure disposed in the first portion, and the metallic shield is electrically connected to the second conductive interconnect structure of the RDL.

14. The system in package of claim 13 , wherein a thickness of the second conductive interconnect structure is greater than a thickness of the first conductive interconnect structures.

15. A semiconductor structure, comprising: a metallic layer; a molding disposed over the metallic layer; a plurality of devices surrounded by the molding; a plurality of metallic shields disposed within the molding, contacted with the metallic layer and isolating the plurality of devices from each other; and a redistribution layer (RDL) disposed over the molding, the plurality of devices and the plurality of metallic shields, wherein the RDL comprises a first portion directly over the molding, a second portion directly over the plurality of the devices, a bottom surface of the first portion is in contact with a surface of the molding, a bottom surface of the second portion is in contact with surfaces of the plurality of devices, the bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other, and a thickness of the first portion is greater than a thickness of the second portion.

16. The semiconductor structure of claim 15 , wherein the RDL comprises: a plurality of first conductive interconnect structures disposed in the second portion; and a plurality of second conductive interconnect structures disposed in the first portion and electrically isolated from the plurality of first conductive interconnect structures.

17. The semiconductor structure of claim 16 , further comprising at least a bond pad, wherein the first conductive interconnect structures electrically connect at least one of the plurality of devices to the bond pad.

18. The semiconductor structure of claim 16 , wherein the plurality of metallic shields are electrically connected to the metallic layer by the plurality of second interconnect conductive structures.

19. The semiconductor structure of claim 18 , wherein the plurality of metallic shields and the metallic layer define a plurality of compartments for isolating the plurality of devices, and the plurality of devices are disposed within the plurality of compartments respectively.

20. The semiconductor structure of claim 16 , wherein a thickness of the second conductive interconnect structures is greater than a thickness of the first conductive interconnect structures.