Non-planar gate thin film transistor

1. An integrated circuit, comprising: a plurality of layers formed on a substrate, the plurality of layers including a first conductor material layer comprising a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first conductor material layer, and a second conductor material layer formed on the ILD, the second conductor material layer comprising a second one of the source or drain; a semiconductive layer formed on a sidewall of the plurality of layers, including on a sidewall of the first conductor material layer, a sidewall of the ILD, and a sidewall of the second conductor material layer; a gate dielectric layer formed on the semiconductive layer; and a gate formed in contact with the gate dielectric layer; wherein the semiconductive layer fully wraps around a portion of the gate that is located in a hole, the semiconductive layer including a cylindrical interior surface and a cylindrical exterior surface, wherein the first conductor material layer, the second conductor material layer, and the gate are made of a same metal material.

2. The integrated circuit of claim 1 , wherein the hole is formed in the plurality of layers, and wherein the sidewall of the plurality of layers comprises a sidewall of the hole.

3. The integrated circuit of claim 2 , wherein the sidewall of the hole is rounded.

4. The integrated circuit of claim 1 , wherein the semiconductive layer comprises at least one of an amorphous semiconductor, a polycrystalline semiconductor, a chalcogenide, or a semiconductive oxide.

5. The integrated circuit of claim 1 , wherein the semiconductive layer comprises at least one of SnO 2 , SnO, CoO, IGZO, ZnO, CuO, Cu 2 O, ITO, IZO, NiO, InO, GaO, Ge or Si.

6. The integrated circuit of claim 1 , wherein the semiconductive layer is doped with one or more metals.

7. The integrated circuit of claim 1 , wherein only a portion of the second conductor material layer comprising the second one of the source or drain is formed over the first conductor material layer comprising the first one of the source or drain in the plurality of layers.

8. The integrated circuit of claim 1 , wherein the substrate comprises peripheral circuitry.

9. An integrated circuit, comprising: a substrate; a first conductor material layer comprising a first one of a source or drain formed above the substrate; a second conductor material layer comprising a second one of the source or drain, the second conductor material layer formed above the first conductor material layer comprising the first one of the source or drain; an inter-layer dielectric (ILD) located between the first and second conductor material layers; a hole formed through the first conductor material layer comprising the first one of the source or drain, the ILD, and the second conductor material layer comprising the second one of the source or drain; and a semiconductive layer formed on a sidewall of the hole, including on a sidewall of the first conductor material layer, a sidewall of the ILD, and a sidewall of the second conductor material layer, wherein the semiconductor layer includes a curved interior surface facing a trench gate located in the hole and curved exterior surface facing the sidewall of the hole, wherein the first conductor material layer, the second conductor material layer, and the trench gate are made of a same metal material.

10. The integrated circuit of claim 9 , wherein the semiconductive layer comprises a shared channel layer for a plurality of transistors.

11. The integrated circuit of claim 9 , wherein the semiconductive layer comprises at least one of an amorphous semiconductor, a polycrystalline semiconductor, a chalcogenide, or a semiconductive oxide.

12. The integrated circuit of claim 9 , wherein the first one of the source or drain is formed on one of a different source or drain, and a second one of the different source or drain is formed on the other one of the different source or drain.

13. The integrated circuit of claim 9 , wherein the semiconductive layer is orthogonal to a planar surface of the substrate.

14. A system, comprising: a processor; and at least one of a network device, a display, or a memory coupled to the processor; wherein the processor includes an integrated circuit, the integrated circuit including: a plurality of layers formed on a substrate, the plurality of layers including a first conductor material layer comprising a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first conductor material layer, and a second conductor material layer formed on the ILD, the second conductor material layer comprising a second one of the source or drain; a semiconductive layer formed on a sidewall of the plurality of layers, including on a sidewall of the first conductor material layer, a sidewall of the ILD, and a sidewall of the second conductor material layer; a gate dielectric layer formed on the semiconductive layer; and a trench gate formed in contact with the gate dielectric layer, wherein said semiconductor layer fully wraps around a portion of the trench gate, wherein the first conductor material layer, the second conductor material layer, and the trench gate are made of a same metal material.

15. The system of claim 14 , wherein the substrate comprises peripheral circuitry.

16. The system of claim 14 , wherein only a portion of the second one of the source or drain is formed over the first one of the source or drain in the plurality of layers.

17. The system of claim 14 , wherein the semiconductive layer comprises at least one of an amorphous semiconductor, a polycrystalline semiconductor, a chalcogenide, or a semiconductive oxide.

18. A method of producing an integrated circuit, the method comprising: forming a first conductor material layer comprising a first one of a source or drain above a substrate; forming an inter-layer dielectric (ILD) above the first conductor material layer comprising the first one of the source or drain; forming a second conductor material layer comprising a second one of the source or drain above the ILD, wherein at least a portion of the second conductor material layer comprising the second one of the source or drain is formed over the first conductor material layer comprising the first one of the source or drain; forming a hole in the portion of the second conductor material layer comprising the second one of the source or drain; forming a semiconductive layer on a sidewall of the hole, including on a sidewall of the first conductor material layer, a sidewall of the ILD, and a sidewall of the second conductor material layer; and forming a gate structure in the hole, the gate structure including a gate dielectric layer disposed in the hole and on the semiconductive layer and a gate disposed on the gate dielectric layer; wherein said semiconductor layer fully wraps around a portion of the gate structure, wherein the first conductor material layer, the second conductor material layer, and the gate are made of a same metal material.

19. The method of claim 18 , wherein a sidewall of the hole is circular.

20. The method of claim 19 , wherein the gate is formed in the hole after formation of the gate dielectric layer, and wherein the method further comprises filling the hole with the metal material to form the gate.

21. The method of claim 18 , wherein the semiconductive layer comprises at least one of an amorphous semiconductor, a polycrystalline semiconductor, a chalcogenide, or a semiconductive oxide.

22. The method of claim 18 , further comprising: forming FEOL (front-end-of-line) circuitry, wherein the substrate comprises said FEOL circuitry; wherein forming the first one of the source or drain, the ILD, the second one of the source or drain, and the hole comprises only BEOL (back-end-of-line) processes.