Gate structure and method

1. A method of forming an integrated circuit structure, the method comprising: forming a fin active region on a semiconductor substrate; forming a dummy gate stack over the fin active region; forming an inter-layer dielectric (ILD) layer around the dummy gate stack; removing the dummy gate stack to form a first trench in the ILD layer; filling the first trench by depositing a gate dielectric layer having a first dielectric material and depositing a conductive material layer on the gate dielectric layer, thereby forming a high-K metal gate stack; performing a first patterning process to the conductive material layer to form a first opening and a second opening; filling the first opening and the second opening with a second dielectric material being different from the first dielectric material in composition, thereby forming a first gate cut feature in the first opening and a second gate cut feature in the second opening; after the filling the first opening and the second opening, performing a second patterning process to the conductive material layer to form a second trench between the first gate cut feature and the second gate cut feature and directly over the fin active region; and filling the second trench with a third dielectric material being different from the first and second dielectric material in composition.

2. The method of claim 1 , wherein the first dielectric material is a high-K dielectric material; the depositing the gate dielectric layer further includes forming an interfacial layer of silicon oxide on the high-K dielectric material; and the depositing the conductive material layer further includes depositing a capping layer; depositing a work-function metal layer over the capping layer; and depositing a bulk metal-containing layer over the work-function metal layer.

3. The method of claim 1 , further comprising: performing a first chemical mechanical polishing (CMP) process to the second dielectric material after the filling the the first opening and the second opening with the second dielectric material such that a top surface of the first gate cut feature is coplanar with a top surface of the high-K metal gate stack.

4. The method of claim 3 , further comprising performing a second CMP process to the third dielectric material after the filling the second trench with the third dielectric material such that a top surface of the third dielectric material is coplanar with the top surface of the high-K metal gate stack.

5. The method of claim 1 , wherein the performing the second patterning process to the conductive material layer to form the second trench includes selectively etching the conductive material layer; and the filling the second trench with the third dielectric material includes filling the third dielectric material directly on the gate dielectric layer.

6. The method of claim 5 , wherein the filling the second trench with the third dielectric material includes filling the third dielectric material on the gate dielectric layer such that the first dielectric material of the gate dielectric layer contacts a sidewall surface and a bottom surface of the third dielectric material.

7. The method of claim 1 , wherein the performing the first patterning process to the conductive material layer to form the first opening and the second opening further includes etching the gate dielectric layer within the first opening and the second opening such that a shallow trench isolation (STI) feature is exposed within the first opening and the second opening.

8. The method of claim 7 , wherein the filling the first opening and the second opening with the second dielectric material includes filling the second dielectric material such that the second dielectric material is directly disposed on the STI feature.

9. The method of claim 8 , wherein the performing the second patterning process to the conductive material layer to form the second trench further includes etching the gate dielectric layer to expose the STI feature within the second trench; and the filling the second trench with the third dielectric material includes filling the third dielectric material such that the third dielectric material is directly disposed on the STI feature.

10. A method of forming an integrated circuit structure, the method comprising: forming a fin active region on a semiconductor substrate; forming a dummy gate stack on the fin active region; forming an inter-layer dielectric (ILD) layer around the dummy gate stack; removing the dummy gate stack to form a first trench in the ILD layer; filling the first trench by a gate dielectric layer having a first dielectric material and a conductive material layer on the gate dielectric layer, thereby forming a high-K metal gate stack having a gate electrode; performing a first patterning process to the conductive material layer to form a second trench; filling the second trench with a second dielectric material, resulting in a first dielectric feature; after the filling the second trench, performing a second patterning process to the conductive material layer to form a third trench directly over the fin active region; and filing the third trench with a third dielectric material, resulting in a second dielectric feature, wherein the second dielectric material is different from the first dielectric material in composition, wherein the gate dielectric layer contacts a bottom surface and a sidewall surface of the first dielectric feature.

11. The method of claim 10 , wherein the third dielectric material is different from the first and second dielectric material in composition, and wherein the gate dielectric layer contacts the second dielectric feature and continuously extends from a bottom surface of the gate electrode to the bottom surface of the first dielectric feature and further extends to a bottom surface of the second dielectric feature.

12. The method of claim 11 , wherein the gate dielectric layer continuously extends from a sidewall surface of the gate electrode to the sidewall surface of the first dielectric feature and further extends to a sidewall surface of the second dielectric feature.

13. The method of claim 11 , wherein the first dielectric material is a high-K dielectric material, the gate dielectric layer further includes an interfacial layer of silicon oxide underlying the high-K dielectric material, and the conductive material layer further includes a capping layer, a work-function metal layer over the capping layer, and a bulk metal-containing layer over the work-function metal layer.

14. The method of claim 11 , further comprising: performing a first chemical mechanical polishing (CMP) process to the second dielectric material after the filling the second trench with the second dielectric material such that the second dielectric feature has a top surface being coplanar with a top surface of the high-K metal gate stack; and performing a second CMP process to the third dielectric material after the filling the third trench with the third dielectric material such that the second dielectric feature is coplanar with the top surface of the high-K metal gate stack.

15. A method of forming an integrated circuit structure, the method comprising: forming a fin active region on a semiconductor substrate; forming a dummy gate stack on the fin active region; forming an inter-layer dielectric (ILD) layer around the dummy gate stack; removing the dummy gate stack to form a first trench in the ILD layer; filling the first trench by depositing a gate dielectric layer including a high-K dielectric material and depositing a conductive material layer on the gate dielectric layer, thereby forming a high-K metal gate stack; performing a first patterning process to the conductive material layer and the gate dielectric layer to form a second trench such that a shallow trench isolation (STI) feature is exposed within the second trench; forming a dielectric feature in the second trench; after the forming the dielectric feature, performing a second patterning process to the conductive material layer and the gate dielectric layer to form a third trench that spans over the fin active region; and forming a dielectric gate in the third trench, wherein a composition of the dielectric feature is different from a composition of the high-K dielectric material.

16. The method of claim 15 , wherein a composition of the dielectric gate is different from a composition of the high-K dielectric material.

17. The method of claim 15 , wherein the dielectric feature is formed to laterally contact the high-K metal gate stack from one side and laterally contact the dielectric gate from an opposite side.

18. The method of claim 17 , wherein the dielectric feature spans between a first edge and a second edge in a first direction; the dielectric gate spans between a third edge and a fourth edge in the first direction; and the third and fourth edges are aligned with the first and second edges, respectively.

19. The method of claim 15 , wherein the dielectric feature is directly disposed on the STI feature.

20. The method of claim 15 , wherein the dielectric feature comprises a first silicon oxide layer and a first silicon nitride layer over the first silicon oxide layer, wherein the the dielectric gate comprises a second silicon nitride layer and a second silicon oxide layer over the second silicon nitride layer.