Semiconductor devices and fabrication methods thereof

1. A method for fabricating a semiconductor device, comprising: forming a first fin structure and a second fin structure adjacent to the first fin structure on a substrate, wherein the first fin structure includes a first sidewall surface and a second sidewall surface opposite to the first sidewall surface, and the first sidewall surface faces to the second fin structure; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of sidewall surfaces of the first fin structure and the second fin structure, and a top surface of the isolation layer is lower than top surfaces of the first fin structure and the second fin structure; forming a first sidewall on the first sidewall surface of the first fin structure and a first modified layer on the second sidewall surface of the first fin structure; forming a first trench in the first fin structure; removing the first modified layer and epitaxially forming the first doped layer in the first trench; after forming the first sidewall, forming a first doped layer in the first fin structure, wherein the first sidewall covers a portion of a sidewall surface of the first doped layer; and forming a second doped layer in the second fin structure.

2. The method according to claim 1 , wherein: the second fin structure includes a third sidewall surface and a fourth sidewall surface opposite to the third sidewall surface, and the third sidewall surface faces to the first fin structure; the method further includes forming a second sidewall on the fourth sidewall surface of the second fin structure prior to forming the second doped layer in the second fin structure, wherein the second sidewall covers a portion of a sidewall surface of the second doped layer.

3. The method according to claim 2 , wherein: the second sidewall is formed after forming the first sidewall; or the second sidewall is formed prior to forming the first sidewall.

4. The method according to claim 2 , wherein: the first sidewall and the second sidewall are formed simultaneously.

5. A method for fabricating a semiconductor device, comprising: forming a first fin structure and a second fin structure adjacent to the first fin structure on a substrate, wherein the first fin structure includes a first sidewall surface and a second sidewall surface opposite to the first sidewall surface, and the first sidewall surface faces to the second fin structure; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of sidewall surfaces of the first fin structure and the second fin structure, and a top surface of the isolation layer is lower than top surfaces of the first fin structure and the second fin structure; forming a first sidewall on the first sidewall surface of the first fin structure; after forming the first sidewall, forming a first doped layer in the first fin structure, wherein the first sidewall covers a portion of a sidewall surface of the first doped layer; and forming a second doped layer in the second fin structure, wherein: the second fin structure includes a third sidewall surface and a fourth sidewall surface opposite to the third sidewall surface, and the third sidewall surface faces to the first fin structure; the method further includes forming a second sidewall on the fourth sidewall surface of the second fin structure prior to forming the second doped layer in the second fin structure, wherein the second sidewall covers a portion of a sidewall surface of the second doped layer, the first sidewall and the second sidewall are formed simultaneously, and simultaneously forming the first sidewall and the second sidewall includes: forming a sidewall material layer on the substrate, wherein the sidewall material layer covers top and sidewall surfaces of the first fin structure and also covers top and sidewall surfaces of the second fin structure; modifying a type of a portion of the sidewall material layer formed on the second sidewall surface of the first fin structure and a portion of the sidewall material layer formed on the third sidewall surface of the second fin structure, such that the portion of the sidewall material layer formed on the second sidewall surface of the first fin structure and the portion of the sidewall material layer formed on the third sidewall surface of the second fin structure contain doped ions and have an etch rate different from an etch rate of an undoped portion of the sidewall material layer, wherein modifying the type of the portion of the sidewall material layer formed on the sidewall surface of the first fin structure and the portion of the sidewall material layer formed on the third sidewall surface of the second fin structure includes an ion doping process; forming the first sidewall on the first sidewall surface of the first fin structure, a first modified layer on the second sidewall surface of the first fin structure, the second sidewall on the fourth surface of the second fin structure, and a second modified layer on the third sidewall surface of the second fin structure by etching back the sidewall material layer until top surfaces of the first fin structure and the second fin structure are exposed, wherein the first modified layer and the second modified layer contain doping ions; and removing the first modified layer and the second modified layer to form the first sidewall on the first sidewall surface of the first fin structure and the second sidewall on the fourth sidewall surface of the second fin structure.

6. The method according to claim 5 , wherein: the ion doping process is an ion implantation process, wherein: doping ions used in the ion implantation process include argon ions or silicon ions, and an implantation dose is a range of approximately 1.0E14 atom/cm 2 to 1.0E17 atom/cm 2 ; and removing the first modified layer and the second modified layer includes a dry etching process or a wet etching process.

7. The method according to claim 6 , wherein: the first modified layer and the second modified layer are removed the wet etching process, wherein: process parameters adopted in the wet etching process include a volume concentration percentage of phosphoric acid in a range of approximately 70% to 95%, and a process temperature in a range of approximately 90° C. to 150° C.

8. The method according to claim 5 , wherein: forming the first doped layer includes forming a first trench in the first fin structure, and epitaxially forming the first doped layer in the first trench, wherein: forming the first trench includes prior to removing the first modified layer, removing a portion of the first fin structure located between the first sidewall and the first modified layer to form a first initial trench, and removing the first modified layer formed on a sidewall surface of the first initial trench to form the first trench.

9. The method according to claim 5 , wherein: forming the second doped layer includes forming a second trench in the second fin structure, and epitaxially forming the second doped layer in the second trench, wherein: forming the second trench includes prior to removing the second modified layer, removing a portion of the second fin structure located between the second sidewall and the second modified layer to form a second initial trench, and removing the second modified layer formed on a sidewall surface of the second initial trench to form the second trench.

10. The method according to claim 4 , wherein simultaneously forming the first sidewall and the second sidewall includes: forming a first initial sidewall on sidewall surfaces of the first fin structure and a second initial sidewall on sidewall surfaces of the second fin structure; modifying a type of a portion of the first initial sidewall formed on the second sidewall surface of the first fin structure and a portion of the second initial sidewall formed on the third sidewall surface of the second fin structure to form a first modified layer on the second sidewall surface of the first fin structure and a second modified layer on the third sidewall surface of the second fin structure, wherein modifying the type of the portion of the first initial sidewall formed on the second sidewall surface of the first fin structure and the portion of the second initial sidewall formed on the third sidewall surface of the second fin structure includes an ion doping process, the first modified layer and the second modified layer contain doping ions, and the first modified layer and the second modified layer have an etch rate different from an etch rate of the first initial sidewall and the second initial sidewall; and removing the first modified layer and the second modified layer to form the first sidewall on the first sidewall surface of the first fin structure and the second sidewall on the fourth sidewall surface of the second fin structure.

11. The method according to claim 10 , wherein forming the first initial sidewall on the sidewall surfaces of the first fin structure and the second initial sidewall on the sidewall surfaces of the second fin structure includes: forming a sidewall material layer on the substrate, wherein the sidewall material layer covers top and sidewall surfaces of the first fin structure and also covers top and sidewall surfaces of the second fin structure; etching back the sidewall material layer to form the first initial sidewall on the sidewall surfaces of the first fin structure and the second initial sidewall on the sidewall surfaces of the second fin structure.

12. The method according to claim 10 , wherein: the ion doping process is an ion implantation process, wherein: doping ions used in the ion implantation process include argon ions or silicon ions, and an implantation dose is a range of approximately 1.0E14 atom/cm 2 to 1.0E17 atom/cm 2 ; and removing the first modified layer and the second modified layer includes a dry etching process or a wet etching process.

13. The method according to claim 12 , wherein: the first modified layer and the second modified layer are removed the wet etching process, wherein: process parameters adopted in the wet etching process include a volume concentration percentage of phosphoric acid in a range of approximately 70% to 95%, and a process temperature in a range of approximately 90° C. to 150° C.

14. The method according to claim 10 , wherein: forming the first doped layer includes forming a first trench in the first fin structure, and epitaxially forming the first doped layer in the first trench, wherein: forming the first trench includes prior to removing the first modified layer, removing a portion of the first fin structure located between the first sidewall and the first modified layer to form a first initial trench, and removing the first modified layer formed on a sidewall surface of the first initial trench to form the first trench.

15. The method according to claim 10 , wherein: forming the second doped layer includes forming a second trench in the second fin structure, and epitaxially forming the second doped layer in the second trench, wherein: forming the second trench includes prior to removing the second modified layer, removing a portion of the second fin structure located between the second sidewall and the second modified layer to form a second initial trench, and removing the second modified layer formed on a sidewall surface of the second initial trench to form the second trench.

16. A method for fabricating a semiconductor device, comprising: forming a first fin structure and a second fin structure adjacent to the first fin structure on a substrate, wherein the first fin structure includes a first sidewall surface and a second sidewall surface opposite to the first sidewall surface, and the first sidewall surface faces to the second fin structure; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of sidewall surfaces of the first fin structure and the second fin structure, and a top surface of the isolation layer is lower than top surfaces of the first fin structure and the second fin structure; forming a first sidewall on the first sidewall surface of the first fin structure; after forming the first sidewall, forming a first doped layer in the first fin structure, wherein the first sidewall covers a portion of a sidewall surface of the first doped layer; and forming a second doped layer in the second fin structure wherein forming the first sidewall includes: forming a protective layer on the second fin structure, wherein the protective layer covers top and sidewall surfaces of the second fin structure; after forming the protective layer, forming a sidewall material layer on the first fin structure and the protective layer, wherein the sidewall material layer covers top and sidewall surfaces of the first fin structure; modifying a type of a portion of the sidewall material layer formed on the second sidewall surface of the first fin structure, such that the portion of the sidewall material layer formed on the second sidewall surface of the first fin structure contains doping ions, wherein the portion of the sidewall material layer containing doping ions has an etch rate different from an etch rate of an undoped portion of the sidewall material layer, and modifying the type of the portion of the sidewall material layer formed on the second sidewall surface of the first fin structure includes an ion doping process; forming the first sidewall on the first sidewall surface of the first fin structure and a first modified layer on the second sidewall surface of the first fin structure by etching back the sidewall material layer until the top surface of the first fin structure is exposed, wherein the first modified layer contains doping ions; and removing the first modified layer.

17. The method according to claim 16 , wherein: the ion doping process is an ion implantation process, wherein: doping ions used in the ion implantation process include argon ions or silicon ions, and an implantation dose is a range of approximately 1.0E14 atom/cm 2 to 1.0E17 atom/cm 2 .

18. The method according to claim 1 , wherein: the second doped layer is formed after forming the first doped layer or the second doped layer is formed prior to forming the first doped layer.

19. The method according to claim 1 , wherein: the first doped layer and the second doped layer are formed simultaneously.

20. The method according to claim 1 , wherein: the first trench is formed between the first sidewall and the first modified layer, and epitaxially forming the first doped layer in the first trench is performed after removing the first modified layer.