A method for manufacturing a display substrate is provided to include: forming an amorphous silicon layer on a base substrate; irradiating at least part of the display region through a mask plate with a laser, to convert a portion of the amorphous silicon layer in the irradiated part of the display region corresponding to channel regions of active layers of transistors into polycrystalline silicon by a laser annealing process; irradiating at least part of the peripheral region with a laser, to convert the amorphous silicon layer in the irradiated part of the peripheral region into polycrystalline silicon; and forming the active layers of the transistors from the amorphous silicon layer which is converted to polycrystalline silicon by a patterning process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a display substrate, which comprises: a display region for display, and a peripheral region outside the display region and comprising a peripheral circuit, wherein, the display region and the peripheral region comprise transistors, and the method for manufacturing a display substrate comprises: forming an amorphous silicon layer on a base substrate; irradiating at least part of the display region with a laser through a mask plate, to only convert a portion of the amorphous silicon layer in the at least part of the display region corresponding to channel regions of active layers of the transistors into polycrystalline silicon by a regional laser annealing process; irradiating at least part of the peripheral region with a laser, to convert all the amorphous silicon layer in the at least part of the peripheral region into polycrystalline silicon; and forming the active layers of the transistors from a part of the amorphous silicon layer which is converted to polycrystalline silicon by a patterning process; wherein the irradiating at least part of the display region with a laser through a mask plate comprises: successively irradiating a plurality of first sub-regions in the display region with the laser through the mask plate, wherein each of the plurality of first sub-regions corresponds to one of the channel regions of the active layers of the transistors, and wherein, each of the channel regions is a region for allowing current to flow between a source and a drain of a transistor when the transistor is turned on.
2. The method for manufacturing a display substrate according to claim 1 , wherein each of the plurality of first sub-regions has a rectangular shape, and has a length and a width each in a range of 1 mm to 1000 mm, and the width is smaller than or equal to the length.
3. The method for manufacturing a display substrate according to claim 1 , wherein the irradiating at least part of the peripheral region with a laser comprises: successively irradiating a plurality of second sub-regions in the peripheral region with the laser, wherein each of the plurality of second sub-regions comprises channel regions of the active layers of the transistors, wherein, each of the channel regions is a region for allowing current to flow between a source and a drain of a transistor when the transistor is turned on.
4. The method for manufacturing a display substrate according to claim 1 , wherein the display substrate comprises an array substrate.
5. The method for manufacturing a display substrate according to claim 2 , wherein any two adjacent first sub-regions of the plurality of first sub-regions have a first interval region therebetween, and the first interval region is located between two corresponding channel regions.
6. The method for manufacturing a display substrate according to claim 5 , wherein the first interval region has a size in a range of 0.001 mm to 10 mm in a direction along which the two first sub-regions adjacent to the first interval region are arranged.
7. The method for manufacturing a display substrate according to claim 3 , wherein each of the plurality of second sub-regions has a rectangular shape, and has a length and a width each in a range of 0.001 mm to 1000 mm, and the width is smaller than or equal to the length.
8. The method for manufacturing a display substrate according to claim 7 , wherein any two adjacent second sub-regions of the plurality of second sub-regions have a second interval region therebetween, and the second interval region is located between two corresponding channel regions.
9. The method for manufacturing a display substrate according to claim 7 , wherein any two adjacent second sub-regions of the plurality of second sub-regions have a first overlapping region which overlaps with the two adjacent second sub-regions, and wherein, in a direction along which the two adjacent second sub-regions are arranged, the first overlapping region has a size smaller than or equal to 50% of a size of the second sub-region.
10. The method for manufacturing a display substrate according to claim 7 , wherein any two adjacent second sub-regions of the plurality of second sub-regions have a second overlapping region which overlaps with the two adjacent second sub-regions, and wherein, in a direction along which the two adjacent second sub-regions are arranged, the second overlapping region has a size greater than 50% of a size of the second sub-region.
11. The method for manufacturing a display substrate according to claim 8 , wherein the second interval region has a size in a range of 0.001 mm to 10 mm in a direction along which the two second sub-regions adjacent to the second interval region are arranged.
12. The method for manufacturing a display substrate according to claim 4 , wherein the peripheral circuit comprises a gate driver circuit.
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September 20, 2019
July 13, 2021
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