Apparatus configured to perform an access operation on a memory cell of an array of memory cells, discharge a control gate of a first field-effect transistor after performing the access operation, discharge a control gate of a second field-effect transistor connected in series between the first field-effect transistor and the memory cell after discharging the control gate of the first field-effect transistor, and discharge a control gate of the memory cell after discharging the control gate of the second field-effect transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: an array of memory cells; and a controller configured to access the array of memory cells; wherein the controller is further configured to: perform an access operation on a memory cell of the array of memory cells; after performing the access operation, discharge a control gate of a first field-effect transistor from a first voltage level to a second voltage level lower than the first voltage level, wherein the first field-effect transistor has a source/drain connected to a node selected from a group consisting of a data line selectively connected to the memory cell and a source selectively connected to the memory cell; after discharging the control gate of the first field-effect transistor, discharge a control gate of a second field-effect transistor from a third voltage level to the second voltage level lower than the third voltage level, wherein the second field-effect transistor is connected in series between the first field-effect transistor and the memory cell; and after discharging the control gate of the second field-effect transistor, discharge a control gate of the memory cell from a fourth voltage level to the second voltage level lower than the fourth voltage level.
2. The apparatus of claim 1 , wherein the first field-effect transistor has a negative threshold voltage and wherein the second field-effect transistor has a positive threshold voltage.
3. The apparatus of claim 1 , wherein the first voltage level and the third voltage level are each less than or equal to the fourth voltage level.
4. The apparatus of claim 1 , wherein the controller is further configured to discharge the control gate of the second field-effect transistor a first period of time after discharging the control gate of the first field-effect transistor, and discharge the control gate of the memory cell a second period of time after discharging the control gate of the second field-effect transistor, wherein the second period of time is shorter than the first period of time.
5. The apparatus of claim 4 , wherein the second period of time is an order of magnitude shorter than the second period of time.
6. An apparatus, comprising: an array of memory cells; and a controller configured to access the array of memory cells; wherein the controller is further configured to: perform an access operation on a plurality of series-connected memory cells of the array of memory cells, wherein the plurality of series-connected memory cells is selectively connected between a source and a data line; after performing the access operation, discharge a control gate of a first field-effect transistor connected in series between the plurality of series-connected memory cells and the source to a reference potential, and discharge a control gate of a second field-effect transistor connected in series between the plurality of series-connected memory cells and the data line to the reference potential, wherein the first field-effect transistor has a source/drain connected to the source and wherein the second field-effect transistor has a source/drain connected to the data line; after discharging the control gates of the first field-effect transistor and the second field-effect transistor, discharge a control gate of a third field-effect transistor connected in series between the first field-effect transistor and the plurality of series-connected memory cells to the reference potential, and discharge a control gate of a fourth field-effect transistor connected in series between the second field-effect transistor and the plurality of series-connected memory cells to the reference potential; and after discharging the control gates of the third field-effect transistor and the fourth field-effect transistor, discharge control gates of the plurality of series-connected memory cells to the reference potential.
7. The apparatus of claim 6 , wherein the first field-effect transistor and the second field-effect transistor each have a negative threshold voltage, and wherein the third field-effect transistor and the fourth field-effect transistor each have a positive threshold voltage.
8. The apparatus of claim 6 , wherein the first field-effect transistor is a source GIDL generator gate, the second field-effect transistor is a drain GIDL generator gate, the third field-effect transistor is a source select gate, and the fourth field-effect transistor is a drain select gate.
9. The apparatus of claim 6 , further comprising: a fifth field-effect transistor connected in series between the third field-effect transistor and the plurality of series-connected memory cells; and a sixth field-effect transistor connected in series between the fourth field-effect transistor and the plurality of series-connected memory cells; wherein the controller is further configured to: discharge a control gate of the fifth field-effect transistor to the reference potential prior to, or concurrently with, discharging the control gate of the third field-effect transistor; and discharge a control gate of the sixth field-effect transistor to the reference potential prior to, or concurrently with, discharging the control gate of the fourth field-effect transistor.
10. The apparatus of claim 6 , wherein the controller is further configured to: bring the control gate of the first field-effect transistor and the control gate of the second field-effect transistor to a particular voltage level higher than the reference potential prior to discharging the control gate of the first field-effect transistor and the control gate of the second field-effect transistor to the reference potential; bring the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor to the particular voltage level prior to discharging the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor connected to the reference potential; and bring the control gates of the plurality of series-connected memory cells to the particular voltage level prior to discharging the control gates of the plurality of series-connected memory cells to the reference potential.
11. The apparatus of claim 10 , further comprising: wherein the controller being configured to bring the control gate of the first field-effect transistor and the control gate of the second field-effect transistor to the particular voltage level comprises the controller being configured to increase a voltage level of the control gate of the first field-effect transistor and increase a voltage level of the control gate of the second field-effect transistor; wherein the controller being configured to bring the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor to the particular voltage level comprises the controller being configured to increase a voltage level of the control gate of the third field-effect transistor and increase a voltage level of the control gate of the fourth field-effect transistor; and wherein the controller being configured to bring the control gates of the plurality of series-connected memory cells to the particular voltage level comprises the controller being configured to decrease voltage levels of the control gates of the plurality of series-connected memory cells.
12. The apparatus of claim 10 , further comprising: wherein the controller being configured to bring the control gate of the first field-effect transistor and the control gate of the second field-effect transistor to the particular voltage level comprises the controller being configured to increase a voltage level of the control gate of the first field-effect transistor and increase a voltage level of the control gate of the second field-effect transistor; wherein the controller being configured to bring the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor to the particular voltage level comprises the controller being configured to decrease a voltage level of the control gate of the third field-effect transistor and decrease a voltage level of the control gate of the fourth field-effect transistor; and wherein the controller being configured to bring the control gates of the plurality of series-connected memory cells to the particular voltage level comprises the controller being configured to decrease voltage levels of the control gates of the plurality of series-connected memory cells.
13. The apparatus of claim 10 , wherein the controller is further configured to bring the control gate of the first field-effect transistor, the control gate of the second field-effect transistor, the control gate of the third field-effect transistor, the control gate of the fourth field-effect transistor, and the control gates of the plurality of series-connected memory cells to the particular voltage level concurrently.
14. The apparatus of claim 6 , wherein the controller is further configured to: discharge the control gate of the first field-effect transistor to the reference potential from a first voltage level higher than the reference potential, and discharge the control gate of the second field-effect transistor to the reference potential from a second voltage level higher than the reference potential; discharge the control gate of the third field-effect transistor connected to the reference potential from a third voltage level higher than the reference potential, and discharge the control gate of the fourth field-effect transistor o the reference potential from a fourth voltage level higher than the reference potential; and discharge the control gates of the plurality of series-connected memory cells to the reference potential from a fifth voltage level higher than the reference potential.
15. The apparatus of claim 14 , wherein the fifth voltage level is higher than each of the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level.
16. The apparatus of claim 15 , wherein the first voltage level and the second voltage level are lower than the third voltage level and the fourth voltage level.
17. An apparatus, comprising: an array of memory cells; and a controller configured to access the array of memory cells; wherein the controller is further configured to: perform a read operation on a selected memory cell of a plurality of series-connected memory cells of the array of memory cells, wherein the plurality of series-connected memory cells is selectively connected between a source and a data line; after performing the read operation, concurrently discharge a control gate of a first field-effect transistor, connected in series between the plurality of series-connected memory cells and the source, and a control gate of a second field-effect transistor, connected in series between the plurality of series-connected memory cells and the data line, to a reference potential, wherein the first field-effect transistor has a source/drain connected to the source and wherein the second field-effect transistor has a source/drain connected to the data line; after discharging the control gates of the first field-effect transistor and the second field-effect transistor, concurrently discharge a control gate of a third field-effect transistor, connected in series between the first field-effect transistor and the plurality of series-connected memory cells, and a control gate of a fourth field-effect transistor, connected in series between the second field-effect transistor and the plurality of series-connected memory cells, to the reference potential; and after discharging the control gates of the third field-effect transistor and the fourth field-effect transistor, concurrently discharge a respective control gate of each memory cell of the plurality of series-connected memory cells to the reference potential.
18. The apparatus of claim 17 , wherein the controller is further configured to bring the control gate of the first field-effect transistor, the control gate of the second field-effect transistor, the control gate of the third field-effect transistor, the control gate of the fourth field-effect transistor, and the respective control gate of each memory cell of the plurality of series-connected memory cells to a particular voltage level prior to discharging to the reference potential.
19. The apparatus of claim 18 , wherein the controller is further configured to concurrently bring the control gate of the first field-effect transistor, the control gate of the second field-effect transistor, the control gate of the third field-effect transistor, the control gate of the fourth field-effect transistor, and the respective control gate of each memory cell of the plurality of series-connected memory cells to the particular voltage level.
20. The apparatus of claim 19 , wherein the controller is further configured to concurrently discharge the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor a first period of time after concurrently discharging the control gate of the first field-effect transistor and the control gate of the second field-effect transistor, and to concurrently discharge the respective control gate of each memory cell of the plurality of series-connected memory cells a second period of time after concurrently discharging the control gate of the third field-effect transistor and the control gate of the fourth field-effect transistor, wherein the second period of time is shorter than the first period of time.
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April 29, 2020
July 20, 2021
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