A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory apparatus comprising: a first set of word lines, each word line of the first set of word lines extending from a first end to a second end to couple a respective row of storage cells of the memory apparatus; a second set of word lines, each word line of the second set of word lines extending from a first end to a second end to couple a respective row of storage cells of the memory apparatus, each word line of the second set corresponds to a word line of the first set; and a connection circuit configured to couple the first end of each word line of the first set of word lines to the first end of a corresponding word line of the second set of word lines and couple the second end of each word line of the first set of word lines to the second end of a corresponding word line of the second set of word lines.
2. The memory apparatus of claim 1 , wherein the connection circuit comprises: a first word line switch configured to connect a selected word line in the first set of word lines and an unselected word line in the second set of word lines to a common driver.
3. The memory apparatus of claim 2 , wherein the connection circuit is configured such that the first word line switch supplies a signal to both the selected word line and the unselected word line.
4. The memory apparatus of claim 3 , further comprising a second word line switch configured to connect the unselected word line in the second set of word lines and the selected word line in the first set of word lines to the common driver.
5. The memory apparatus of claim 4 , further comprising an external conductive link between one of the word lines in the first set of word lines and the corresponding word line in the second set of word lines.
6. The memory apparatus of claim 4 , further comprising a trench that separates the word lines of the first set of word lines from the word lines of the second set of word lines and an internal conductive link between one of the word lines in the first set of word lines and the corresponding word line in the second set of word lines.
7. The memory apparatus of claim 6 , further comprising; an erase block comprising the first set of word lines and the second set of word lines; and a die controller configured to erase the erase block in a single erase operation.
8. The memory apparatus of claim 1 , comprising a first erase block comprising the first set of word lines and a second erase block comprising the second set of word lines and further comprising a three-dimensional array of the storage cells organized into a plurality of erase blocks that includes the first erase block and the second erase block, the first erase block positioned adjacent to the second erase block within the three- dimensional array.
9. An apparatus comprising: a three-dimensional array of NAND strings coupled to word lines, the three- dimensional array comprising a selected erase block and an unselected erase block with a trench between the selected erase block and the unselected erase block; a word line interconnect configured to electrically couple each word line of the selected erase block to a corresponding word line of the unselected erase block, the corresponding word line positioned in a common layer of the three-dimensional array, the word line interconnect including an external conductive link that couples a selected word line of the selected erase block to an unselected word line of the unselected erase block outside of the three-dimensional array; a connection circuit configured to selectively couple one or more of the word lines of the selected erase block and one or more of the word lines of the unselected erase block to a common driver; and a die controller configured to bias the NAND strings within the selected erase block and bias NAND strings within the unselected erase block in order to execute a storage operation on storage cells of the selected erase block and mitigate effects of the storage operation on storage cells of the unselected erase block.
10. The apparatus of claim 9 , further comprising a first source line coupled to the selected erase block and a second source line coupled to the unselected erase block and wherein the die controller is configured to bias the NAND strings of the selected erase block and the NAND strings of the unselected erase block to execute an erase operation on the storage cells of the selected erase block.
11. The apparatus of claim 9 , wherein the word line interconnect comprises a trace that spans the trench to connect each word line of the selected erase block to a corresponding word line of the unselected erase block and wherein the connection circuit comprises: a first word line switch configured to connect the word line in the selected erase block and the corresponding word line in the unselected erase block to the common driver; and a second word line switch configured to connect the corresponding word line in the unselected erase block and the word line in the selected erase block to the common driver.
12. The apparatus of claim 11 , wherein the die controller is configured to activate the first word line switch and the second word line switch substantially simultaneously.
13. The apparatus of claim 9 wherein the connection circuit is further configured to selectively couple the common driver to first and second ends of the word lines of the selected and unselected erase blocks.
14. The apparatus of claim 9 wherein the word line interconnect comprises an internal conductive link formed during a fabrication process that forms a selected word line and an unselected word line of the unselected erase block within the three-dimensional array.
15. A method comprising: turning drain select gates of NAND strings off to float the NAND strings; applying a read voltage to a selected word line of a selected erase block from both ends of the selected word line, the read voltage applied concurrently to a corresponding word line of the unselected erase block from both ends of the corresponding word line by way of a word line interconnect; applying a pass voltage to unselected word lines of the selected erase block from both ends of the unselected word lines, the pass voltage applied concurrently to unselected word lines of the unselected erase block from both ends by way of a word line interconnect; and sensing a read state for storage cells on the selected word line, wherein the floating NAND strings mitigates resistive-capacitive delay on the selected word line and unselected word lines.
16. The method of claim 15 , further comprising, activating a first word line switch configured to connect the selected word line in the selected erase block and the corresponding word line in the unselected erase block to a common driver; and activating a second word line switch configured to connect the the corresponding word line in the unselected erase block and the selected word line in the selected erase block to the common driver.
17. The method of claim 15 , wherein a connection circuit couples each word line of the selected erase block and each corresponding word line of the unselected erase block to a common driver configured to supply the read voltage and the pass voltage.
18. The method of claim 15 , wherein applying the read voltage to the selected word line of the selected erase block from both ends of the selected word line comprises connecting a first driver to the selected word line on a first end of the selected word line and connecting a second driver to the selected word line on a second end of the selected word line.
19. The method of claim 18 , wherein sensing the read state for storage cells of the selected word line comprises exclusively activating sense amplifiers of the selected erase block.
20. The method of claim 15 , further comprising applying a common voltage to a first source line connected to the selected erase block and to a second source line connected to the unselected erase block.
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June 18, 2019
August 3, 2021
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