A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A Controller Integrated Circuit (IC) adapted for controlling Memory ICs, the Controller IC comprising: external interface terminals, comprising: a plurality of sets of bus connection terminals adapted to be electrically coupled to corresponding functional terminals on at least one Memory IC via a collection of electrical bus conductors, wherein a first set of the bus connection terminals of the Controller IC is adapted to transport data between the Controller IC and the Memory IC through one or more bus conductors in a data bus group using a burst mode during a data transfer time, and wherein a second set of the bus connection terminals of the Controller IC is configured to transmit, to the Memory IC through a single conductor, a serial command during the data transfer time such that the serial command can direct operation of the Memory IC by providing commands, address and data transfer control information from the Controller IC.
2. The Controller IC of claim 1 wherein said first set of the bus connection terminals is further adapted to transmit, during a command transfer time, a parallel command to the Memory IC through the one or more bus conductors in said data bus group.
3. A Memory Interface Circuit adapted to be incorporated within a Memory Controller, the Memory Interface Circuit comprising: a plurality of external terminals adapted to be coupled to bus connection terminals of the Memory Controller; one or more functional terminals adapted to be electrically coupled to a corresponding one of a plurality of sets of bus connection terminals on the Memory Controller via a collection of electrical bus conductors, wherein a first functional terminal is adapted to receive data from the Controller IC through one or more bus conductors in a data bus group using a burst mode during a data transfer time, and wherein a second functional terminal is configured to transmit, from the Memory Interface Circuit through a single conductor, a serial command during the data transfer time such that the serial command can direct the operation of the Memory Controller by providing commands, address and data transfer control information from the Memory Interface Circuit.
4. The Memory Interface Circuit of claim 3 wherein the first functional terminal is further adapted to transmit, during a command transfer time, a parallel command to the Memory Controller through one or more bus conductors in said data bus set.
5. A Memory Integrated Circuit (IC) primarily adapted for memory storage comprising a plurality of external interface terminals, the plurality of external interface terminals comprising: a plurality of sets of bus connection terminals adapted to be electrically coupled to corresponding functional terminals on a Controller IC via a collection of electrical bus conductors, wherein a first set of the bus connection terminals of the Memory IC is adapted to transport data between the Controller IC and the Memory IC through one or more bus conductors in a data bus group using a burst mode during a data transfer time, and wherein a second set of the bus connection terminals of the Memory IC is configured to receive, from the Controller IC through a single conductor, a serial command during the data transfer time such that the serial command can direct the operation of the Memory IC by providing commands, address and data transfer control information from the Memory Controller IC.
6. The Memory IC of claim 5 wherein the Memory IC is a Non Volatile Memory.
7. The Memory IC of claim 5 wherein the Memory IC is a Random Access Memory (RAM).
8. The Memory IC of claim 5 wherein the Memory IC is a Dynamic Random Access Memory (DRAM).
9. The Memory IC of claim 5 , wherein said first group of the bus connection terminals is further adapted to receive, during a command transfer time, a parallel command from one or more bus conductors in said data bus set.
10. The Memory IC of claim 8 wherein said first group of the bus connection terminals is further adapted to receive, during a command transfer time, a parallel command from one or more bus conductors in said data bus set.
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April 7, 2020
August 10, 2021
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