A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: at least one unit layer stack located over a substrate, wherein the at least one unit layer stack comprises a metallic source layer, a channel-level insulating layer, a metallic drain layer, and a device-isolation-level insulating layer; a plurality of memory openings vertically extending through the at least one unit layer stack; and memory opening fill structures located within a respective one of the plurality of memory openings, wherein each of the memory opening fill structures comprises a tubular ferroelectric dielectric layer and at least one two-dimensional electron gas channel vertically extending between the metallic source layer and the metallic drain layer of the at least one unit layer stack.
2. The memory device of claim 1 , wherein the channel-level insulating layer contacts an outer cylindrical sidewall of a respective one of the at least one two-dimensional electron gas channel.
3. The memory device of claim 1 , wherein the tubular ferroelectric dielectric layer contacts a cylindrical surface of the metallic source layer and a cylindrical surface of the metallic drain layer.
4. The memory device of claim 1 , wherein each of the memory opening fill structures comprises a word line located over an inner cylindrical sidewall of the tubular ferroelectric dielectric layer and vertically extending through each metallic source layer and each metallic drain layer within the at least one unit layer stack.
5. The memory device of claim 1 , wherein the at least one unit layer stack comprises a vertical stack of a plurality of the at least one unit layer stacks.
6. The memory device of claim 1 , wherein the tubular ferroelectric dielectric layer comprises: a first ferroelectric dielectric layer having a first band gap energy; and a second dielectric layer having a second band gap energy that is greater than the first band gap energy and located between the first ferroelectric dielectric layer and the two-dimensional electron gas channel.
7. The memory device of claim 6 , wherein: the first ferroelectric dielectric layer comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.
8. The memory device of claim 1 , wherein the tubular ferroelectric dielectric layer comprises a two-dimensional Van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP 2 S 6 , a-In 2 Se 3 , g-SbP, g-SbAs, or Group IV monochalcogenide material having a formula of MX in which M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.
9. The memory device of claim 1 , wherein the at least one two-dimensional electron gas channel comprises a metal dichalcogenide channel.
10. The memory device of claim 9 , wherein: the at least one two-dimensional electron gas channel has a lateral thickness in a range from 1 monolayer to 5 monolayers and includes the two-dimensional electron gas therein; and the at least one two-dimensional cylindrical electron gas channel comprises a material having a composition of Mo 1-x W x S 2-y Se y , wherein x is in a range from 0 to 1, and y is independent of x and is in a range from 0 to 2.
11. A memory device comprising: a two-dimensional electron gas channel located on a substrate; a source region and a drain region located at end portions of the two-dimensional electron gas channel; a two-dimensional Van der Waals ferroelectric material layer located on the two-dimensional electron gas channel and comprising a ferroelectric material selected from CuInP 2 S 6 , a-In 2 Se 3 , g-SbP, g-SbAs, or Group IV monochalcogenide material having a formula of MX in which M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and at least one gate electrode located over the two-dimensional Van der Waals ferroelectric material layer.
12. The memory device of claim 11 , further comprising a channel-side interfacial dielectric layer comprising hafnium aluminum oxide, hafnium oxide or aluminum oxide contacting the substrate and the two-dimensional electron gas channel.
13. The memory device of claim 11 , further comprising a ferroelectric-side interfacial dielectric layer comprising hafnium aluminum oxide, hafnium oxide or aluminum oxide contacting the two-dimensional Van der Waals ferroelectric material layer and the at least one gate electrode.
14. The memory device of claim 11 , wherein: the substrate comprises a semiconductor material layer; and the source region and the drain region includes a respective doped portion of the semiconductor material layer.
15. The memory device of claim 11 , wherein: the source region and the drain region comprise a respective portion of a two-dimensional electron gas channel layer including a material of the two-dimensional electron gas channel and additionally including dopant atoms; a source-contact via structure contacts a top surface of the source region; and a drain-contact via structure contacts a top surface of the drain region.
16. The memory device of claim 11 , wherein the at least one gate electrode comprises a plurality of gate electrodes that are arranged along a direction connecting the source region and the drain region to provide a NAND memory device, or are arranged along a direction perpendicular to the direction connecting the source region and the drain region to provide a NOR memory device.
17. A ferroelectric memory device, comprising: a channel; a gate electrode; a ferroelectric element located between the gate electrode and the channel, wherein the ferroelectric element comprises two-dimensional Van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP 2 S 6 , a-In 2 Se 3 , g-SbP, g-SbAs, or Group IV monochalcogenide material having a formula of MX in which M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and a first interfacial dielectric layer located between the ferroelectric element and the gate electrode.
18. The ferroelectric memory device of claim 17 , wherein the first interfacial dielectric layer comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide.
19. The ferroelectric memory device of claim 17 , wherein the memory device comprises a monolithic three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the gate electrode comprises one of the electrically conductive layers; a memory opening vertically extending through the alternating stack, wherein the channel comprises a two-dimensional electron gas channel located inside memory opening; ferroelectric memory elements located between the channel and the electrically conductive layers, wherein the ferroelectric element comprises one of the ferroelectric elements; and a dielectric core surrounded by the channel.
20. The ferroelectric memory device of claim 19 , further comprising a second interfacial dielectric layer contacting the two-dimensional electron gas channel and the dielectric core and comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide.
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February 24, 2020
August 31, 2021
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