Patentable/Patents/US-11115693
US-11115693

Source clock recovery in wireless video systems

PublishedSeptember 7, 2021
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Systems, apparatuses, and methods for performing efficient video transmission are disclosed. In a video processing system, a transmitter sends encoded pixel data to a receiver. The receiver stores the encoded pixel data in a buffer at an input data rate. A decoder of the receiver reads the pixel data from the buffer at an output data rate. Each of a transmitter and the receiver maintains a respective synchronization counter. When detecting a start of a frame, each of the transmitter and the receiver stores a respective frame start count as a copy of a current value of the respective synchronization counter. The transmitter sends its frame start count to the receiver. The receiver determines a difference between the respective frame start counts, and adjusts the decoding rate based on the difference.

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A receiver comprising: a transceiver configured to receive encoded pixels of frames; and logic configured to: detect a start of frame and a corresponding transmitter counter value in wirelessly received data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame; capture a receiver counter value responsive to a decoder of the receiver detecting the start of frame; compare the transmitter counter value to the receiver counter value; and adjust a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

2

2. The receiver as recited in claim 1 , wherein the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and the receiver counter value is a copy of a value of a TSF counter in the receiver.

3

3. The receiver as recited in claim 2 , wherein the copy of the value of the synchronization counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

4

4. The receiver as recited in claim 3 , wherein the logic is further configured to add an estimated propagation latency value to the transmitter counter value prior to determining said difference.

5

5. The receiver as recited in claim 3 , wherein in response to determining a decoder in the receiver is enabled, the logic is further configured to capture the receiver counter value by capturing a copy of the value of the synchronization counter in the receiver at a detected start of a frame in the receiver.

6

6. The receiver as recited in claim 3 , wherein in response to determining a decoder in the receiver is disabled, the logic is further configured to capture the receiver counter value by capturing a copy of the value of the synchronization counter in the receiver at a time of detecting the corresponding transmitter counter value in wirelessly received data.

7

7. The receiver as recited in claim 6 , wherein in further response to determining the decoder is disabled, the logic is further configured to enable the decoder after a delay based on a difference between the corresponding transmitter counter value and the captured receiver counter value.

8

8. The receiver as recited in claim 1 , wherein the receiver is configured to: receive the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and periodically receive a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.

9

9. The receiver as recited in claim 1 , wherein to adjust the pixel decoding data rate, the logic is further configured to: reduce the pixel decoding data rate, in response to determining the transmitter counter value is greater than the receiver counter value; and increase the pixel decoding data rate, in response to determining the transmitter counter value is less than the receiver counter value.

10

10. A method, comprising: receiving, by a transceiver of a receiver, encoded pixels of frames from a transmitter; detecting, by logic of the receiver, a start of frame and a corresponding transmitter counter value in wirelessly received data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame; capturing, by the logic, a receiver counter value responsive to a decoder of the receiver detecting the start of frame; comparing, by the logic, the transmitter counter value to the receiver counter value; and adjusting, by the logic, a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

11

11. The method as recited in claim 10 , wherein the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and the receiver counter value is a copy of a value of a TSF counter in the receiver.

12

12. The method as recited in claim 11 , wherein the copy of the value of the TSF counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

13

13. The method as recited in claim 12 , further comprising adding an estimated propagation latency value to the transmitter counter value prior to determining said difference.

14

14. The method as recited in claim 10 , wherein to adjust the pixel decoding data rate, the method further comprises: reducing the pixel decoding data rate, in response to determining the transmitter counter value is greater than the receiver counter value; and increasing the pixel decoding data rate, in response to determining the transmitter counter value is less than the receiver counter value.

15

15. The method as recited in claim 10 , further comprising: receiving the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and periodically receiving a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.

16

16. A system comprising: a transmitter configured to: encode pixels of frames; and transmit the encoded pixels of frames; and a receiver configured to: receive wireless data including the encoded pixels of frames from the transmitter; detect a start of frame and a corresponding transmitter counter value in the received wireless data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame; capture a receiver counter value responsive to a decoder of the receiver detecting the start of frame; compare the transmitter counter value to the receiver counter value; and adjust a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

17

17. The system as recited in claim 16 , wherein the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and the receiver counter value is a copy of a value of a TSF counter in the receiver.

18

18. The system as recited in claim 17 , wherein the copy of the value of the TSF counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

19

19. The system as recited in claim 18 , wherein the receiver is further configured to add an estimated propagation latency value to the transmitter counter value prior to determining said difference.

20

20. The system as recited in claim 16 , wherein the receiver is further configured to: receive the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and periodically receive a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

March 27, 2019

Publication Date

September 7, 2021

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “Source clock recovery in wireless video systems” (US-11115693). https://patentable.app/patents/US-11115693

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.