A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, wherein the barrier layer is titanium nitride; a superconducting bump bond consisting of indium on the barrier layer; and a second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
2. The device of claim 1 , wherein the first interconnect pad is aluminum.
3. The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device.
4. The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element.
5. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate.
6. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate.
7. The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 30, 2019
September 28, 2021
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