Patentable/Patents/US-11139801
US-11139801

Power-on reset circuit

PublishedOctober 5, 2021
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A power-on reset (POR) circuit includes first, second and third resistors. A first transistor has a first control terminal and first and second voltage terminals. A second transistor has a second control terminal and third and fourth voltage terminals. A third transistor has a third control terminal and fifth and sixth voltage terminals. The first control terminal is coupled via the first resistor to the second voltage terminal. The third voltage terminal is coupled via the second resistor to the first voltage terminal. The second control terminal is coupled via the third resistor to the fourth voltage terminal. The third control terminal is coupled to the third voltage terminal. The fifth voltage terminal is coupled to the first control terminal. A voltage buffer is coupled to the fifth voltage terminal.

Patent Claims
5 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A power-on reset (POR) circuit comprising: first, second and third resistors; a first transistor having a first control terminal and first and second voltage terminals, the first control terminal coupled via the first resistor to the second voltage terminal; a second transistor having a second control terminal and third and fourth voltage terminals, the third voltage terminal coupled via the second resistor to the first voltage terminal, and the second control terminal coupled via the third resistor to the fourth voltage terminal; a third transistor having a third control terminal and fifth and sixth voltage terminals, the third control terminal coupled to the third voltage terminal, and the fifth voltage terminal coupled to the first control terminal; and a voltage buffer coupled to the fifth voltage terminal.

2

2. The POR circuit of claim 1 , wherein the sixth voltage terminal is coupled to a ground terminal.

3

3. The POR circuit of claim 2 , further comprising a fourth transistor coupled between the sixth voltage terminal and the ground terminal.

4

4. The POR circuit of claim 3 , wherein the first voltage terminal is coupled to a voltage source terminal.

5

5. The POR circuit of claim 2 , wherein the first voltage terminal is coupled to a voltage source terminal.

Classification Codes (CPC)

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Patent Metadata

Filing Date

September 28, 2020

Publication Date

October 5, 2021

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Cite as: Patentable. “Power-on reset circuit” (US-11139801). https://patentable.app/patents/US-11139801

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