Semiconductor package and method of manufacturing the same

1. A semiconductor package comprising: a redistribution structure comprising a redistribution insulating layer and a redistribution pattern, the redistribution insulating layer including a first insulating layer; a first semiconductor chip provided on a first surface of the redistribution insulating layer and electrically connected to the redistribution pattern; and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad, wherein the redistribution pattern is formed on a top surface of the first insulating layer and the lower electrode pad is formed on a bottom surface of the first insulating layer, and wherein the redistribution pattern includes a seed layer, and the seed layer contacts the top surface of the first insulating layer and a top surface of the lower electrode pad.

2. The semiconductor package of claim 1 , wherein the thickness of the second portion of the lower electrode pad is between about 10% and about 30% of a total thickness of the lower electrode pad.

3. The semiconductor package of claim 1 , wherein a sidewall of the second portion of the lower electrode pad is exposed to the outside of the redistribution insulating layer.

4. The semiconductor package of claim 1 , wherein the redistribution structure further comprises a conductive via pattern electrically connected to the lower electrode pad through a portion of the redistribution insulating layer.

5. The semiconductor package of claim 4 , wherein a width of the conductive via pattern is gradually narrower in a first direction, in which the first direction directs from the first surface to the second surface of the redistribution insulating layer.

6. The semiconductor package of claim 4 , wherein the seed layer surrounds a sidewall of the conductive via pattern.

7. The semiconductor package of claim 1 , wherein the first semiconductor chip comprises a chip pad provided on a surface facing the first surface of the redistribution insulating layer, and the semiconductor package further comprises a chip connection terminal provided between a portion of the redistribution pattern on the first surface of the redistribution insulating layer and the chip pad of the first semiconductor chip.

8. The semiconductor package of claim 1 , further comprising an external connection terminal on a bottom surface of the lower electrode pad.

9. The semiconductor package of claim 8 , wherein the bottom surface of the lower electrode pad is flat.

10. The semiconductor package of claim 1 , further comprising a molding layer covering a side surface of the first semiconductor chip; and a conductive pillar penetrating the molding layer and electrically connected to the redistribution pattern.

11. A semiconductor package comprising: a redistribution insulating layer comprising a first surface and a second surface opposite to each other; a first conductive line pattern in the redistribution insulating layer; a second conductive line pattern on the first surface of the redistribution insulating layer; a lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer; a first conductive via pattern extending between the first conductive line pattern and the lower electrode pad and in contact with the lower electrode pad; a second conductive via pattern extending between the second conductive line pattern and the first conductive line pattern; and a semiconductor chip disposed on the redistribution insulating layer and electrically connected to the second conductive line pattern, wherein widths of the first conductive via pattern and the second conductive via pattern are each gradually narrower in a first direction, wherein the first direction is from the first surface of the redistribution insulating layer toward the second surface of the redistribution insulating layer.

12. The semiconductor package of claim 11 , wherein a thickness of the second portion of the lower electrode pad is between about 1 μm, and about 3 μm.

13. The semiconductor package of claim 11 , wherein a sidewall of the second portion of the lower electrode pad is exposed to the outside of the redistribution insulating layer, and a height of a sidewall of the first portion of the lower electrode pad is greater than a height of the sidewall of the second portion of the lower electrode pad.

14. The semiconductor package of claim 11 , further comprising: a first seed layer surrounding a sidewall of the first conductive via pattern and provided between the first conductive via pattern and the lower electrode pad; and a second seed layer surrounding a sidewall of the second conductive via pattern and provided between the second conductive via pattern and the first conductive via pattern.

15. The semiconductor package of claim 11 , further comprising a chip connection terminal disposed between the second conductive line pattern and the semiconductor chip; and an underfill material layer disposed between the semiconductor chip and the first surface of the redistribution insulating layer and surrounding the chip connection terminal.

16. The semiconductor package of claim 11 , further comprising an external connection terminal on a bottom surface of the second portion of the lower electrode pad, wherein the bottom surface of the second portion of the lower electrode pad is flat.

17. A semiconductor package comprising: a redistribution structure comprising a plurality of insulating layers, a plurality of conductive line patterns disposed on an upper surface of each of the plurality of insulating layers, and a plurality of conductive via patterns penetrating at least one of the plurality of insulating layers and connected to at least one of the plurality of conductive line patterns; a semiconductor chip on an upper surface of the redistribution structure; a chip connection terminal interposed between the semiconductor chip and a conductive line pattern of an uppermost layer of the plurality of conductive line patterns; an underfill material layer surrounding the chip connection terminal between the semiconductor chip and the redistribution structure; a molding layer covering at least a portion of the semiconductor chip; a lower electrode pad on a bottom surface of the redistribution structure; and an external connection terminal on the lower electrode pad, wherein the lower electrode pad comprises a first portion embedded in a lowermost insulating layer of the plurality of insulating layers and a second portion protruding from the lowermost insulating layer, and a thickness of the second portion of the lower electrode pad is less than a thickness of the first portion of the lower electrode pad, and wherein the lower electrode pad has a rectangular cross-sectional view.

18. The semiconductor package of claim 17 , wherein the plurality of conductive via patterns each have a shape that gradually narrows in a direction from an upper surface of the redistribution structure toward a lower surface of the redistribution structure.

19. The semiconductor package of claim 17 , wherein a portion of the plurality of conductive via patterns is in contact with the lower electrode pad.