Multi-level buffers for biasing of radio frequency (RF) switches are provided. An RF switching circuit that includes a field-effect transistor (FET) switch, an impedance, and a multi-level buffer that provides a switch control voltage to a gate of the FET through the impedance is disclosed. The multi-level buffer receives a control signal to turn on or off the FET switch. Additionally, the multi-level buffer is implemented with stacked inverters that operate using different clock signal phases to pulse the switch control voltage in response to a transition of the control signal to thereby shorten a delay in switching the FET switch.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A radio frequency (RF) switching circuit comprising: a field-effect transistor (FET) switch including a gate; an impedance; and a multi-level buffer having an output terminal connected to the gate of the FET through the impedance, wherein the multi-level buffer comprises a first inverter configured to receive a first clock signal phase and powered by a first supply voltage and a second supply voltage less than the first supply voltage, a second inverter configured to receive a second clock signal phase and powered by the second supply voltage and a third supply voltage less than the second supply voltage, a third inverter configured to receive a third clock signal phase and powered by an output of the first inverter and an output of the second inverter, and a first output switch connected between the output terminal and an output of the third inverter.
2. The RF switching circuit of claim 1 , wherein the multi-level buffer is configured to generate a turn-on pulse of the switch control voltage in response to a transition of a control signal from an off state to an on state.
3. The RF switching circuit of claim 2 , wherein the multi-level buffer is configured to generate the turn-on pulse by controlling the switch control voltage with the first supply voltage for a duration of the turn-on pulse, and thereafter to a steady-state on voltage by controlling the switch control voltage with the second supply voltage.
4. The RF switching circuit of claim 1 , wherein the first output switch is a p-type FET having a gate controlled by the output of the second inverter.
5. The RF switching circuit of claim 1 , wherein the multi-level buffer further comprises a fourth inverter configured to receive a fourth clock signal phase and powered by the second supply voltage and the third supply voltage, and a second output switch connected to the output terminal and controlled by an output of the fourth inverter.
6. The RF switching circuit of claim 5 , wherein the multi-level buffer further comprises a fifth inverter configured to receive a fifth clock signal phase and powered by the third supply voltage and a fourth supply voltage less than the third supply voltage, and a sixth inverter configured to receive a sixth clock signal phase and powered by the output of the fourth inverter and an output of the fifth inverter, wherein an output of the sixth inverter is connected to the output terminal through the second output switch.
7. The RF switching circuit of claim 6 , wherein the second output switch is an n-type FET having a gate controlled by the output of the fourth inverter.
8. The RF switching circuit of claim 6 , wherein the multi-level buffer is configured to generate a turn-off pulse of the switch control voltage in response to a transition of the control signal from the on state to the off state.
9. The RF switching circuit of claim 8 , wherein the multi-level buffer is configured to generate the turn-off pulse by controlling the switch control voltage with the fourth supply voltage for a duration of the turn-off pulse, and thereafter to a steady-state off voltage by controlling the switch control voltage with the third supply voltage.
10. The RF switching circuit of claim 6 , wherein the multi-level driver further comprises a first level-shifter configured to drive an input of the first inverter and a second level-shifter configured to drive an input of the fifth inverter.
11. The RF switching circuit of claim 1 , wherein the first inverter, the second inverter, the third inverter, and the first output switch are implemented using a plurality of FETs.
12. The RF switching circuit of claim 11 , wherein a voltage difference between the first supply voltage and the third supply voltage exceeds a voltage rating of the plurality of transistors.
13. The RF switching circuit of claim 1 , wherein the FET switch is an n-type metal oxide semiconductor (NMOS) switch or a p-type metal oxide semiconductor (PMOS) switch.
14. The RF switching circuit of claim 1 , wherein the impedance comprises a gate resistor.
15. The RF switching circuit of claim 1 , wherein the multi-level driver further comprising a timing circuit configured to receive a control signal, and to generate a plurality of clock signal phases including the first clock signal phase, the second clock signal phase, and the third clock signal phase.
16. A multi-level buffer for driving a transistor gate, the multi-level buffer comprising: an output terminal; a first inverter configured to receive a first clock signal phase and powered by a first supply voltage and a second supply voltage less than the first supply voltage; a second inverter configured to receive a second clock signal phase and powered by the second supply voltage and a third supply voltage less than the second supply voltage; a third inverter configured to receive a third clock signal phase and powered by an output of the first inverter and an output of the second inverter; and a first output switch connected between the output terminal and an output of the third inverter.
17. The multi-level buffer of claim 16 , wherein the first output switch is a p-type FET having a gate controlled by the output of the second inverter.
18. The multi-level buffer of claim 16 , wherein the multi-level buffer further comprises a fourth inverter configured to receive a fourth clock signal phase and powered by the second supply voltage and the third supply voltage, and a second output switch connected to the output terminal and controlled by an output of the fourth inverter.
19. The multi-level buffer of claim 16 , wherein the multi-level buffer further comprises a fifth inverter configured to receive a fifth clock signal phase and powered by the third supply voltage and a fourth supply voltage less than the third supply voltage, and a sixth inverter configured to receive a sixth clock signal phase and powered by the output of the fourth inverter and an output of the fifth inverter, wherein an output of the sixth inverter is connected to the output terminal through the second output switch.
20. A method of radio frequency (RF) switching, the method comprising: providing a first clock signal phase to an input of a first inverter that is powered by a first supply voltage and a second supply voltage less than the first supply voltage; providing a second clock signal phase to an input of a second inverter that is powered by the second supply voltage and a third supply voltage less than the second supply voltage; providing a third clock signal phase to an input of a third inverter that is powered by an output of the first inverter and an output of the second inverter; controlling an output voltage at an output terminal using a first output switch connected between the output terminal and an output of the third inverter; and providing the output voltage to a gate of a field-effect transistor (FET) switch through an impedance.
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October 12, 2020
October 19, 2021
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