Contact formation for stacked vertical transport field-effect transistors

1. A method of forming a semiconductor structure, comprising: forming a stacked vertical transport field-effect transistor structure comprising one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor; forming at least one vertical via in the stacked vertical transport field-effect transistor structure, the at least one vertical via being spaced apart from the one or more vertical fins of the stacked vertical transport field-effect transistor structure; forming at least one horizontal via extending from the at least one vertical via to at least one source/drain region of at least one of the upper and lower vertical transport field-effect transistors of the stacked vertical transport field-effect transistor structure; forming a contact liner in the at least one horizontal via; forming a barrier layer on sidewalls of the at least one vertical via and on sidewalls of the contact liner, wherein the barrier layer comprises an electrically conducting material; and forming a contact material over the barrier layer in the at least one vertical via.

2. The method of claim 1 , wherein forming the at least one vertical via comprises: patterning a mask layer to expose a portion of a top surface of the stacked vertical transport field-effect transistor, the exposed portion of the top surface being spaced apart from the one or more vertical fins of the stacked vertical transport field-effect transistor structure; and etching the stacked vertical transport field-effect transistor to expose sidewalls of one or more sacrificial layers disposed adjacent the at least one source/drain region.

3. The method of claim 2 , wherein forming the at least one horizontal via comprises removing the one or more sacrificial layers.

4. The method of claim 1 , wherein forming the contact liner comprises: depositing the contact liner using a conformal deposition process to pinch off a space formed by the at least one horizontal via; and etching back the contact liner to remove portions of the contact liner formed on a bottom surface of the at least one vertical via, the sidewalls of the at least one vertical via, and a top surface of the stacked vertical transport field-effect transistor structure.

5. The method of claim 4 , wherein the contact liner comprises at least one of titanium, nickel, cobalt and platinum.

6. The method of claim 4 , wherein forming the barrier layer comprises depositing the barrier layer using a conformal deposition process.

7. The method of claim 6 , wherein the barrier layer comprises titanium nitride.

8. The method of claim 6 , wherein forming the contact material over the barrier layer in the at least one vertical via comprises: filling the contact material; and planarizing the contact material and the barrier layer to the top surface of the stacked vertical transport field-effect transistor structure.

9. The method of claim 8 , wherein the contact material comprises at least one of tungsten and cobalt.

10. The method of claim 1 , wherein forming the at least one horizontal via comprises: forming a first horizontal via extending from the at least one vertical via to a first top source/drain region for a lower vertical transport field-effect transistor of a first one of the one or more vertical fins; forming a second horizontal via extending from the at least one vertical via to a first bottom source/drain region of an upper vertical transport field-effect transistor of the first vertical fin; and forming a third horizontal via extending from the at least vertical via to a second bottom source/drain region of an upper vertical transport field-effect transistor of a second one of the one or more vertical fins.

11. The method of claim 10 , wherein the contact liner and the contact material provide a shared output contact for a NAND logic gate.

12. The method of claim 1 , wherein forming the stacked vertical transport field-effect transistor structure further comprises: forming one or more first bottom source/drain regions for the one or more lower vertical transport field-effect transistors surrounding a first portion of the first semiconductor layer of the one or more vertical fins; forming a shallow trench isolation layer surrounding the one or more first bottom source/drain regions; forming a first bottom spacer over the one or more first bottom source/drain regions and the shallow trench isolation layer and surrounding a second portion of the first semiconductor layer of the one or more vertical fins; forming one or more first gate stacks for the one or more lower vertical transport field-effect transistors over the first bottom spacer surrounding a third portion of the first semiconductor layer of the one or more vertical fins; forming a first interlayer dielectric over the first bottom spacer surrounding the one or more first gate stacks; forming a first top spacer over the first interlayer dielectric surrounding a fourth portion of the first semiconductor layer of the one or more vertical fins; forming one or more first top source/drain regions for the one or more lower vertical transport field-effect transistors over the first top spacer surrounding a fifth portion of the first semiconductor layer of the one or more vertical fins; and forming a second interlayer dielectric over the first top spacer and surrounding the one or more first top source/drain regions and the isolation layer of the one or more vertical fins.

13. The method of claim 12 , wherein forming the stacked vertical transport field-effect transistor further comprises: forming one or more second bottom source/drain regions for the one or more upper vertical transport field-effect transistors surrounding a first portion of the second semiconductor layer of the one or more vertical fins; forming a third interlayer dielectric surrounding the one or more second bottom source/drain regions and a second portion of the second semiconductor layer of the one or more vertical fins; forming one or more second gate stacks for the one or more upper vertical transport field-effect transistors surrounding a third portion of the second semiconductor layer of the one or more vertical fins; forming a fourth interlayer dielectric surrounding the one or more second gate stacks; forming a second top spacer over the one or more second gate stacks and the fourth interlayer dielectric and surrounding a third portion of the second semiconductor layer of the one or more vertical fins; forming one or more second top source/drain regions over a top surface of the second semiconductor layer of the one or more vertical fins; and forming a fifth interlayer dielectric over the second top spacer and surrounding the one or more second top source/drain regions.

14. A semiconductor structure, comprising: a stacked vertical transport field-effect transistor structure comprising one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor; at least one vertical via in the stacked vertical transport field-effect transistor structure, the at least one vertical via being spaced apart from the one or more vertical fins of the stacked vertical transport field-effect transistor structure; at least one horizontal via extending from the at least one vertical via to at least one source/drain region of at least one of the upper and lower vertical transport field-effect transistors of the stacked vertical transport field-effect transistor structure; a contact liner disposed in the at least one horizontal via; a barrier layer disposed on sidewalls of the contact liner and the at least one vertical via, wherein the barrier layer comprises an electrically conducting material; and a contact material disposed over the barrier layer in the at least one vertical via.

15. The semiconductor structure of claim 14 , wherein the at least one horizontal via comprises: a first horizontal via extending from the at least one vertical via to a first top source/drain region for a lower vertical transport field-effect transistor of a first one of the one or more vertical fins; a second horizontal via extending from the at least one vertical via to a first bottom source/drain region of an upper vertical transport field-effect transistor of the first vertical fin; and a third horizontal via extending from the at least vertical via to a second bottom source/drain region of an upper vertical transport field-effect transistor of a second one of the one or more vertical fins.

16. The semiconductor structure of claim 15 wherein the contact liner and the contact material provide a shared output contact for a NAND logic gate.

17. The semiconductor structure of claim 14 , further comprising: one or more first bottom source/drain regions for the one or more lower vertical transport field-effect transistors surrounding a first portion of the first semiconductor layer of the one or more vertical fins; a shallow trench isolation layer surrounding the one or more first bottom source/drain regions; a first bottom spacer disposed over the one or more first bottom source/drain regions and the shallow trench isolation layer and surrounding a second portion of the first semiconductor layer of the one or more vertical fins; one or more first gate stacks for the one or more lower vertical transport field-effect transistors disposed over the first bottom spacer surrounding a third portion of the first semiconductor layer of the one or more vertical fins; a first interlayer dielectric disposed over the first bottom spacer surrounding the one or more first gate stacks; a first top spacer disposed over the first interlayer dielectric surrounding a fourth portion of the first semiconductor layer of the one or more vertical fins; one or more first top source/drain regions for the one or more lower vertical transport field-effect transistors disposed over the first top spacer surrounding a fifth portion of the first semiconductor layer of the one or more vertical fins; and a second interlayer dielectric disposed over the first top spacer and surrounding the one or more first top source/drain regions and the isolation layer of the one or more vertical fins.

18. The semiconductor structure of claim 17 , further comprising: one or more second bottom source/drain regions for the one or more upper vertical transport field-effect transistors surrounding a first portion of the second semiconductor layer of the one or more vertical fins; a third interlayer dielectric surrounding the one or more second bottom source/drain regions and a second portion of the second semiconductor layer of the one or more vertical fins; one or more second gate stacks for the one or more upper vertical transport field-effect transistors surrounding a third portion of the second semiconductor layer of the one or more vertical fins; a fourth interlayer dielectric surrounding the one or more second gate stacks; a second top spacer disposed over the one or more second gate stacks and the fourth interlayer dielectric and surrounding a third portion of the second semiconductor layer of the one or more vertical fins; one or more second top source/drain regions disposed over a top surface of the second semiconductor layer of the one or more vertical fins; and a fifth interlayer dielectric disposed over the second top spacer and surrounding the one or more second top source/drain regions.

19. An integrated circuit comprising: a stacked vertical transport field-effect transistor structure comprising: one or more vertical fins each comprising a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper vertical transport field-effect transistor; at least one vertical via spaced apart from the one or more vertical fins; at least one horizontal via extending from the at least one vertical via to at least one source/drain region of at least one of the upper and lower vertical transport field-effect transistors; a contact liner disposed in the at least one horizontal via; a barrier layer disposed on sidewalls of the contact liner and the at least one vertical via, wherein the barrier layer comprises an electrically conducting material; and a contact material disposed over the barrier layer in the at least one vertical via.

20. The integrated circuit of claim 19 , wherein the at least one horizontal via comprises: a first horizontal via extending from the at least one vertical via to a first top source/drain region for a lower vertical transport field-effect transistor of a first one of the one or more vertical fins; a second horizontal via extending from the at least one vertical via to a first bottom source/drain region of an upper vertical transport field-effect transistor of the first vertical fin; and a third horizontal via extending from the at least vertical via to a second bottom source/drain region of an upper vertical transport field-effect transistor of a second one of the one or more vertical fins.