Memory with select line voltage control

1. A memory comprising: a plurality of memory cells; a plurality of word lines, each word line of the plurality of word lines is coupled to a subset of memory cells of a plurality of subsets of the plurality of memory cells; a plurality of select lines, each select line of the plurality of select lines is coupled a subset of memory cells of the plurality of subsets; a plurality of word line drivers, each word line driver of the plurality of word line drivers providing an asserted word line voltage on a word line of the plurality of word lines when memory cells of a subset coupled to the word line are to be accessed during a memory operation, wherein the each word line driver is configured to enable a first conductive path between a select line of the plurality of select lines coupled to the subset and a first voltage setting terminal for biasing the select line when an asserted word line voltage is provided on the each word line and is configured to enable a second conductive path between the select line to a second voltage setting terminal for biasing the select line when an asserted word line voltage is not provided on the each word line.

2. The memory of claim 1 wherein each word line driver of the plurality of word line drivers includes two transistors coupled in series, wherein a select line of the plurality of select lines associated with the each word line driver is coupled to a node located between the two transistors coupled in series, wherein the first conductive path includes a first transistor of the two transistors and a second conductive path includes a second transistor of the two transistors.

3. The memory of claim 2 wherein the first transistor includes a control electrode that is responsive to the word line associated with the each word line driver, wherein the first transistor includes a first current electrode coupled to the select line and a second current terminal coupled to the first voltage setting terminal.

4. The memory of claim 2 wherein the second transistor includes a first current electrode coupled to the select line and a second current terminal coupled to the second voltage setting terminal.

5. The memory of claim 4 wherein the second transistor includes a control electrode coupled to a node that is coupled to a control electrode of a third transistor for coupling a word line associated with the each word line driver to a word line voltage setting terminal.

6. The memory of claim 1 further comprising a plurality of transistors each including a control electrode coupled to a word line coupled to a subset of memory cells of the plurality of subsets, the plurality of transistor are made conductive by an asserted word line voltage on the word line to bias a select line of the plurality of select lines coupled to the subset by the first voltage setting terminal.

7. The memory of claim 1 wherein the memory is configured to place the second voltage setting terminal at a first voltage to bias unselected select lines of the plurality of select lines when a memory operation is being performed to permanently write a value to at least one cell of the memory cells and is configured to place the second voltage setting terminal at a second voltage different than the first voltage to bias unselected select lines of the plurality of select lines when a memory operation is being performed to non-permanently write a value to at least one cell of the memory cells.

8. The memory of claim 1 wherein for at least one type of memory operation, the second voltage setting terminal is configured to provide a nonground voltage to bias unselected select lines of the plurality of select lines during a memory operation.

9. The memory of claim 1 wherein the memory cells are characterized as resistive memory cells.

10. A method of operating a memory, the memory including a plurality of subsets of memory cells, a plurality of word lines, and a plurality of select lines, wherein each word line of the plurality of word lines is coupled to a subset of the plurality of subsets and each select line of the plurality of select lines is coupled a subset of the plurality of subsets, the method comprising: performing a first memory operation including accessing memory cells of a first subset of memory cells of the plurality of subsets, the performing the first memory operation including providing an asserted word line voltage on a word line of the plurality of word lines coupled to the first subset and concurrently enabling a first conductive path between a select line of the plurality of select lines coupled to the subset and a first voltage setting terminal to bias the select line at a selected select line voltage; performing a second memory operation including accessing memory cells of a second subset of memory cells of the plurality of subsets and not accessing memory cells of the first subset, wherein performing the second memory operation includes providing a nonasserted word line voltage on the word line and concurrently enabling a second conductive path between the select line and a second voltage setting terminal to bias the select line at an unselected select line voltage, wherein the first conductive path is not enabled when the nonasserted word line voltage is provided on the word line wherein the first memory operation is characterized as a one-time programmable write operation that permanently writes values to the memory cells accessed of the first subset of memory cells.

11. The method of claim 10 wherein the unselected select line voltage is a nonground voltage.

12. The method of claim 11 further comprising: performing a third memory operation including accessing memory cells of a third subset of memory cells of the plurality of subsets and not accessing memory cells of the first subset, wherein the performing the third memory operation includes providing a nonasserted word line voltage on the word line and concurrently enabling the second conductive path between the select line and the second voltage setting terminal to bias the select line at a second unselected select line voltage that is different from the unselected select line voltage.

13. The method of claim 12 wherein the second memory operation is a one-time programmable write operation that permanently writes values to the memory cells accessed of the second subset of memory cells and the third memory operation is a non one-time programmable write operation that does not permanently write values to the memory cells accessed of the third subset of memory cells.

14. The method of claim 10 wherein the second memory operation is characterized as a non one-time programmable write operation that does not permanently write values to the memory cells accessed of the second subset of memory cells.

15. A memory comprising: a plurality of memory cells; a plurality of word lines, each word line of the plurality of word lines is coupled to a subset of memory cells of a plurality of subsets of the plurality of memory cells; a plurality of select lines, each select line of the plurality of select lines is coupled to a subset of memory cells of the plurality of subsets; a plurality of word line drivers, each word line driver of the plurality of word line drivers is associated with a subset of the plurality of subsets, a word line of the plurality of word lines, and a select line of the plurality of select lines, wherein during an access to memory cells of its associated subset, each word line driver of the plurality of word line drivers is configured to provide an asserted word line voltage on its associated word line and concurrently enable a first conductive path between its associated select line and a first voltage setting terminal to provide a selected select line voltage on its associated select line, wherein each word line driver of the plurality of word line drivers is configured to provide a nonasserted word line voltage on its associated word line and concurrently enable a second conductive path between its associated select line and a second voltage setting terminal to provide a select line voltage on its associated select line.

16. The memory of claim 15 wherein the memory cells are characterized as resistive memory cells.

17. The memory of claim 15 further comprising a plurality of bit lines, each bit line of the plurality of bit lines is coupled to only one memory cell of a subset of the plurality of subsets, wherein the plurality of select lines are characterized as a plurality of source lines.

18. The memory of claim 15 , wherein the memory is configured to provide different unselected select line voltages from the second voltage setting terminal for at least two different types of memory accesses performed by the memory.

19. The memory of claim 15 wherein for at least one type of memory operation, the second voltage setting terminal is configured to provide a nonground voltage to bias unselected select lines of the plurality of select lines during a memory operation.