Semiconductor package and manufacturing process thereof

1. A semiconductor package comprising: an encapsulated semiconductor die; a redistribution layer, disposed on the encapsulated semiconductor die and electrically coupled to the encapsulated semiconductor die, wherein the redistribution layer comprises an outmost dielectric material layer, an outmost metallization layer having at least one first contact pad, and a surface coating layer sandwiched between the outmost dielectric material layer and the outmost metallization layer, and the at least one first contact pad includes a first concave portion exposed from the surface coating layer; and at least one conductive element disposed on the first concave portion of the at least one first contact pad, wherein the surface coating layer is lower than a top surface of the outmost dielectric material layer, and the at least one conductive element is in contact with the outmost dielectric material layer, the surface coating layer and the first concave portion.

2. The semiconductor package as claimed in claim 1 , wherein the outmost metallization layer further comprises second contact pads, and each of the second contact pads has a second concave portion exposed from the surface coating layer.

3. The semiconductor package as claimed in claim 2 , further comprising a second semiconductor die disposed on the redistribution layer and electrical connectors disposed on the second concave portions of the second contact pads, wherein the second semiconductor die disposed on the electrical connectors are electrically connected to the redistribution layer through the electrical connectors.

4. The semiconductor package as claimed in claim 3 , wherein the electrical connectors are in contact with the outmost dielectric material layer, the surface coating layer and the second concave portions.

5. The semiconductor package as claimed in claim 3 , wherein the second semiconductor die includes a high voltage chip or a voltage modulation chip.

6. The semiconductor package as claimed in claim 1 , further comprising a front redistribution layer disposed under the encapsulated semiconductor die and electrically connected with the encapsulated semiconductor die.

7. The semiconductor package as claimed in claim 6 , further comprising at least one through via electrically connecting the redistribution layer and the front redistribution layer.

8. The semiconductor package as claimed in claim 1 , wherein the encapsulated semiconductor die includes one or more fingerprint sensor.

9. The semiconductor package as claimed in claim 1 , wherein the surface coating layer extends beyond a periphery of the first concave portion of the at least one first contact pad.

10. A semiconductor package comprising: a first die encapsulated in a molding material; a redistribution layer, disposed on the molding material and electrically connected with the first die, wherein the first die is disposed at a first side of the redistribution layer; a second die, disposed at a second side of the redistribution layer opposite to the first side and electrically connected with the redistribution layer through electrical connectors therebetween; and conductive elements, disposed at the second side of the redistribution layer, wherein the redistribution layer includes an outmost dielectric material layer, an outmost metallization layer having first contact pads and second contact pads, and a surface coating layer sandwiched between the outmost dielectric material layer and the outmost metallization layer, the first contact pad has a first concave portion exposed from the surface coating layer, and the second contact pad has a second concave portion exposed from the surface coating layer, and wherein the first concave portion, the surface coating layer and a top surface of the outmost dielectric material layer are located at different levels, the conductive elements are in contact with the outmost dielectric layer, the surface layer and the first concave portions of the first contact pads, and the electrical connectors are in contact with the outmost dielectric layer, the surface layer and the second concave portions of the second contact pads.

11. The semiconductor package as claimed in claim 10 , wherein the surface coating layer extends beyond a periphery of the first concave portion and beyond a periphery of the second concave portion.

12. The semiconductor package as claimed in claim 10 , further comprising a front-side redistribution layer disposed under the first die and on the molding compound and electrically connected with the first die.

13. The semiconductor package as claimed in claim 12 , further comprising a protection layer located on the front-side redistribution layer, wherein the first die includes at least one fingerprint sensor.

14. The semiconductor package as claimed in claim 10 , wherein the surface coating layer comprises titanium and copper.

15. A manufacturing process for a semiconductor package, comprising: providing a carrier; forming a first redistribution layer on the carrier, wherein forming the first redistribution layer comprises forming a surface coating layer, a dielectric material layer and a metallization layer having at least one contact pad on the carrier; disposing a first die on the first redistribution layer; encapsulating the first die in a molding material; forming a second redistribution layer on the molding material and on a front surface of the first die, wherein the second redistribution layer is electrically connected to the first die and the first redistribution layer; disposing a protection layer on the second redistribution layer; debonding the carrier from the first redistribution layer to expose the surface coating layer and the dielectric material layer; etching the surface coating layer and the at least one contact pad of the first redistribution layer to form a concave portion in the at least one contact pad, wherein the concave portion, the etched surface coating layer and a top surface of the dielectric material layer are at different levels, and; and disposing at least one conductive element on the concave portion of the at least one contact pad, wherein the at least one conductive element is electrically connected to the first redistribution layer.

16. The process as claimed in claim 15 , wherein forming the first redistribution layer on the carrier comprises: forming a polymer dielectric material layer on the carrier; patterning the polymer dielectric material layer to form openings penetrating through the polymer dielectric material layer; forming the surface coating layer over the polymer dielectric material layer and conformally covering the openings; forming the metallization layer on the surface coating layer and the polymer dielectric material layer to fill the openings; and patterning the metallization layer and the surface coating layer.

17. The process as claimed in claim 15 , wherein prior to forming the second redistribution layer, the process further comprises: planarizing the molding material to expose the front surface of the first die.

18. The process as claimed in claim 15 , wherein etching the surface coating layer and the at least one contact pad of the first redistribution layer comprises: dry etching the surface coating layer covering the at least one contact pad of the metallization layer of the first redistribution layer to remove a portion of the surface coating layer; and wet etching the surface coating layer and the at least one contact pad to form the concave portion in the at least one contact pad.

19. The process as claimed in claim 18 , wherein the surface coating layer comprises titanium and copper, dry etching the surface coating layer comprises performing a titanium dry etching process and wet etching the at least one contact pad comprises performing a titanium wet etching process.

20. The process as claimed in claim 18 , wherein the concave portion of the at least one contact pad exposes a portion of a sidewall of the surface coating layer, and a distance from a lowest point of the concave portion of the at least one contact pad to a front surface of the first redistribution layer in a normal direction of the front surface of the first redistribution layer is greater than a height of the exposed portion of the sidewall of the surface coating layer in the normal direction.