Patentable/Patents/US-11171110
US-11171110

Backside metalization with through-wafer-via processing to allow use of high q bondwire inductances

PublishedNovember 9, 2021
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A flip-chip integrated circuit die includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias at the rear side of the die.

Patent Claims
14 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A flip-chip integrated circuit semiconductor die comprising: a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry; at least two through-wafer vias extending at least partially though the semiconductor die and having portions at a rear side of the semiconductor die; and a bond wire external to the semiconductor die and extending between and electrically coupling the portions of the at least two through-wafer vias to one another at the rear side of the semiconductor die.

2

2. The flip-chip integrated circuit semiconductor die of claim 1 further comprising backside metallization disposed on at least the portions of the at least two through-wafer vias at the rear side of the semiconductor die, the bond wire being electrically coupled to the portions of the at least two through-wafer vias through the backside metallization.

3

3. The flip-chip integrated circuit semiconductor die of claim 1 wherein the active circuitry forms at least a portion of a power amplifier.

4

4. The flip-chip integrated circuit semiconductor die of claim 3 wherein the bond wire is an inductive element in a matching circuit for the power amplifier.

5

5. The flip-chip integrated circuit semiconductor die of claim 3 wherein the bond wire exhibits a quality factor of at least 60.

6

6. The flip-chip integrated circuit semiconductor die of claim 1 wherein the active circuitry includes radio frequency circuitry.

7

7. An electronics module including the flip-chip integrated circuit semiconductor die of claim 1 .

8

8. An electronic device including the electronics module of claim 7 .

9

9. A radio frequency device including the electronics module of claim 7 .

10

10. An electrical structure comprising: a first integrated circuit semiconductor die including a front side having active circuitry formed therein, a plurality of bond pads in electrical communication with the active circuitry, and at least two through-wafer vias extending at least partially though the semiconductor die and having portions at a rear side of the semiconductor die; a second integrated circuit semiconductor die including a rear side mounted on the rear side of the first integrated circuit semiconductor die and having bond pads disposed on a front side thereof; and at least one bond wire external to the first integrated circuit semiconductor die and the second integrated circuit semiconductor die and electrically coupling at least one of the at least two through-wafer vias of the first integrated circuit semiconductor die to at least one bond pad of the second integrated circuit semiconductor die.

11

11. The electrical structure of claim 10 wherein the second integrated circuit semiconductor die includes active circuitry in the front side thereof.

12

12. The electronic structure of claim 10 wherein the bond wire is an inductive element in a matching circuit for active circuitry in one of the first integrated circuit semiconductor die and the second integrated circuit semiconductor die.

13

13. The electronic structure of claim 12 wherein the bond wire exhibits a quality factor of at least 60.

14

14. The electrical structure of claim 12 wherein the active circuitry includes a power amplifier.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

April 20, 2018

Publication Date

November 9, 2021

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Cite as: Patentable. “Backside metalization with through-wafer-via processing to allow use of high q bondwire inductances” (US-11171110). https://patentable.app/patents/US-11171110

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