A semiconductor arrangement includes a well region, a transistor over the well region, a conductive line in conductive contact with a first source/drain region of the transistor and having a sidewall in conductive contact with a sidewall of the well region, and a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region. A method includes forming a well region in a semiconductor layer. A first fin and a second fin are formed over the well region. A first spacer is formed on the first fin and a second spacer is formed on the second fin. A portion of the well region positioned between the first spacer and the second spacer is removed to define a trench. A liner layer is formed in the trench, and a conductive line is formed in the trench over the liner layer. The conductive line conductively contacts the well region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor arrangement, comprising: a well region; a transistor over the well region; a conductive line having a sidewall in conductive contact with a sidewall of the well region, wherein the conductive line is further in conductive contact with a first source/drain region of the transistor; a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region; and a contact extending through the well region and contacting a bottom of the liner layer.
2. The semiconductor arrangement of claim 1 , wherein: a channel of the transistor is defined in a fin, the channel extends in a first direction between the first source/drain region of the transistor and a second source/drain region of the transistor, and the conductive line extends in the first direction such that the conductive line extends parallel to the fin.
3. The semiconductor arrangement of claim 1 , wherein the liner layer is disposed between a bottom surface of the conductive line and the well region.
4. The semiconductor arrangement of claim 1 , comprising: an isolation structure disposed between a gate structure of the transistor and the conductive line.
5. The semiconductor arrangement of claim 1 , wherein: a channel of the transistor is defined in a fin, and the semiconductor arrangement comprises an isolation structure disposed over the conductive line and laterally between the conductive line and the fin.
6. The semiconductor arrangement of claim 1 , comprising: a dielectric spacer between the sidewall of the well region and a sidewall of the contact.
7. The semiconductor arrangement of claim 1 , wherein the liner layer comprises a metal.
8. The semiconductor arrangement of claim 1 , wherein the liner layer is a silicide layer.
9. The semiconductor arrangement of claim 1 , wherein the liner layer directly contacts the sidewall of the conductive line and the sidewall of the well region.
10. The semiconductor arrangement of claim 9 , wherein the liner layer directly contacts a bottom surface of the conductive line and a surface of the well region underlying the bottom surface of the conductive line.
11. The semiconductor arrangement of claim 1 , comprising: an isolation structure overlying the conductive line, wherein a gate electrode of the transistor overlies the isolation structure.
12. A semiconductor arrangement, comprising: a first well region comprising a first type of dopant; a second well region abutting the first well region and comprising a second type of dopant different than the first type of dopant; a first cell configured to perform a logic function and comprising: a first transistor over the first well region; and a second transistor over the second well region; a first liner layer at least partially embedded in the first well region at a cell boundary of the first cell and a second cell; and a first conductive line overlying the first liner layer and separated from the first well region by the first liner layer, wherein the first conductive line is electrically coupled to the first transistor.
13. The semiconductor arrangement of claim 12 , wherein a bottom surface of the first conductive line is below a top surface of the first well region.
14. The semiconductor arrangement of claim 12 , wherein the first transistor and the second transistor share a common gate electrode.
15. The semiconductor arrangement of claim 14 , comprising: a second liner layer at least partially embedded in the second well region at a cell boundary of the first cell and a third cell spaced apart from the second cell by the first cell; and a second conductive line overlying the second liner layer and separated from the second well region by the second liner layer, wherein the second conductive line is electrically coupled to the second transistor.
16. A semiconductor arrangement, comprising: a well region; a transistor over the well region; a conductive line having a sidewall in conductive contact with a sidewall of the well region, wherein the conductive line is further in conductive contact with a first source/drain region of the transistor; and a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region, wherein the liner layer directly contacts the sidewall of the conductive line and the sidewall of the well region.
17. The semiconductor arrangement of claim 16 , wherein: a channel of the transistor is defined in a fin, the channel extends in a first direction between the first source/drain region of the transistor and a second source/drain region of the transistor, and the conductive line extends in the first direction such that the conductive line extends parallel to the fin.
18. The semiconductor arrangement of claim 16 , wherein the liner layer is disposed between a bottom surface of the conductive line and the well region.
19. The semiconductor arrangement of claim 16 , comprising: an isolation structure disposed between a gate structure of the transistor and the conductive line.
20. The semiconductor arrangement of claim 16 , wherein: a channel of the transistor is defined in a fin, and the semiconductor arrangement comprises an isolation structure disposed over the conductive line and laterally between the conductive line and the fin.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 26, 2019
November 9, 2021
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