The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a sense line; an access line; and a memory cell, wherein the memory cell includes: a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line; a second transistor having a control gate, wherein: the control gate of the second transistor is coupled to the access line; a first node of the second transistor is coupled to the sense line; and a second node of the second transistor is coupled to the floating gate of the first transistor; and a diode coupled to the sense line and a node of the first transistor.
2. The apparatus of claim 1 , wherein the diode is configured to prevent a current from flowing through the memory cell when the memory cell is an unselected cell during a program operation.
3. The apparatus of claim 1 , wherein the apparatus includes: a source line coupled to an additional node of the first transistor; and a common source plate coupled to the source line.
4. The apparatus of claim 1 , wherein the memory cell is configured to store a data state using the first transistor and the second transistor.
5. The apparatus of claim 1 , wherein: the first transistor is a p-type metal-oxide-semiconductor (PMOS) transistor; and the second transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.
6. The apparatus of claim 1 , wherein: an n-type material of the diode is in contact with a p-type channel of the first transistor; and a p-type material of the diode is in contact with an n-type channel of the second transistor.
7. The apparatus of claim 6 , wherein the n-type channel of the second transistor is in contact with the sense line and the floating gate of the first transistor.
8. The apparatus of claim 1 , wherein: an n-type material of the diode is in contact with a p-type channel of the first transistor; a p-type material of the diode is in contact with an n-doped material; and the n-doped material is in contact with an n-type channel of the second transistor and the sense line.
9. An apparatus, comprising: a plurality of sense lines; a plurality of access lines; and an array of memory cells, wherein each respective memory cell of the array includes: a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to one of the access lines; a second transistor having a control gate, wherein: the control gate of the second transistor is coupled to the one of the of access lines; a first node of the second transistor is coupled to one of the plurality of sense lines; and a second node of the second transistor is coupled to the floating gate of the first transistor; and a diode coupled to the one of the plurality of sense lines and a node of the first transistor.
10. The apparatus of claim 9 , wherein: the apparatus includes: a common source plate; and a plurality of source lines coupled to the common source plate; and an additional node of the first transistor of each respective memory cell of the array is coupled to one of the plurality of source lines.
11. The apparatus of claim 10 , wherein the common source plate is a ground plate.
12. The apparatus of claim 9 , wherein the diode of each respective memory cell of the array is in series with the one of the plurality of sense lines and the node of the first transistor of that respective memory cell.
13. The apparatus of claim 9 , wherein the diode of each respective memory cell of the array is a bipolar junction diode.
14. A method of operating memory, comprising: applying, during a program operation being performed on the memory, a voltage to a sense line, wherein the sense line is coupled to: a diode of a memory cell, wherein the diode is coupled to a node of a first transistor of the memory cell; and a first node of a second transistor of the memory cell, wherein a second node of the second transistor is coupled to a floating gate of the first transistor; and preventing, by the diode of the memory cell, current from flowing from the sense line through the first transistor of the memory cell while the voltage is being applied to the sense line during the program operation.
15. The method of claim 14 , wherein the method includes: applying, during a sense operation being performed on the memory, a voltage to an access line, wherein the access line is coupled to: a control gate of the first transistor of the memory cell; and a control gate of the second transistor of the memory cell; and allowing, by the diode of the memory cell, current to flow through the first transistor of the memory cell to the sense line while the voltage is being applied to the access line during the sense operation.
16. The method of claim 15 , wherein the current that flows through the first transistor of the memory cell to the sense line first flows from a common source plate to a source line coupled to the common source plate, and from the source line to an additional node of the first transistor.
17. A method of operating memory, comprising: selecting, during a program operation being performed on an array of memory cells, a memory cell of a subset of memory cells of the array, wherein each respective memory cell of the subset includes: a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to one of a plurality of access lines coupled to the subset of memory cells; a second transistor having a control gate, wherein: the control gate of the second transistor is coupled to the one of the access lines; a first node of the second transistor is coupled to a sense line coupled to the subset of memory cells; and a second node of the second transistor is coupled to the floating gate of the first transistor; and a diode coupled to the sense line and a node of the first transistor; and preventing, by the diode of each respective unselected memory cell of the subset, current from flowing from the sense line through the first transistor of that respective unselected memory cell.
18. The method of claim 17 , wherein selecting the memory cell of the subset comprises: applying a voltage to the one of the access lines to which the control gates of the first and second transistors of that memory cell are coupled; and applying a voltage to the sense line.
19. The method of claim 18 , wherein the voltage applied to the one of the access lines is a voltage that exceeds a threshold voltage associated with the second transistor.
20. The method of claim 18 , wherein the voltage applied to the sense line is a voltage that is less than the voltage applied to the one of the access lines.
21. The method of claim 18 , wherein the voltage applied to the sense line is 0 Volts.
22. The method of claim 17 , wherein the method includes: selecting, during a sense operation being performed on the array of memory cells, a memory cell of the subset of memory cells of the array; and allowing, by the diode of the memory cell of the subset selected during the sense operation, current to flow through the first transistor of the memory cell of the subset selected during the sense operation to the sense line.
23. The method of claim 22 , wherein selecting the memory cell of the subset during the sense operation comprises: applying a negative voltage to the one of the access lines to which the control gates of the first and second transistors of that memory cell are coupled; and applying a negative voltage to the sense line.
24. The method of claim 23 , wherein the negative voltage applied to the one of the access lines and the negative voltage applied to the sense line are a same voltage.
25. The method of claim 17 , wherein the subset of memory cells comprises a column of memory cells of the array.
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May 18, 2020
November 23, 2021
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