Data verifying method, chip, and verifying apparatus

1. A data verifying method, comprising: providing a first encoder for at least one processing circuit of a chip; encoding, through the first encoder, at least one transmitting data of a to-be-test circuit of the at least one processing circuit to generate at least one first parity data, wherein the at least one transmitting data is a computing result generated by the to-be-test circuit; transmitting the at least one first parity data without the at least one transmitting data, wherein the at least one first parity data is used for data verification of the at least one transmitting data; providing a decoder for the at least one processing circuit of the chip; computing, through the decoder, at least one second parity data with at least one previous updating data to generate at least one updating indicator; updating the at least one previous updating data at corresponding position recorded in the at least one updating indicator, to generate at least one current updating data, wherein the at least one previous updating data and the at least one current updating data are used for generating the at least one transmitting data.

2. The data verifying method according to claim 1 , wherein the step of encoding the at least one transmitting data of the to-be-test circuit comprises: encoding the at least transmitting data based on error detection code or error correction code, wherein each of the at least one first parity data is an encoded result of the at least one transmitting data.

3. The data verifying method according to claim 1 , wherein the step of encoding the at least one transmitting data of the to-be-test circuit comprises: combining a plurality of the first parity data to form a first combined data, wherein a length of the first combined data is not longer than a length of one of the at least one transmitting data, and the step of transmitting the at least one first parity data comprises: transmitting the first combined data.

4. The data verifying method according to claim 1 , wherein before the step of encoding the at least one transmitting data of the to-be-test circuit, the data verifying method further comprises: receiving at least one updating data; and processing, through the to-be-test circuit, the at least one updating data to generate the at least one transmitting data.

5. The data verifying method according to claim 1 , wherein after the step of transmitting the at least one first parity data, the data verifying method further comprises: providing a second encoder out of the chip; encoding, through the second encoder, at least one expected data to generate at least one third parity data; and verifying consistency between one of the at least one first parity data and corresponding third parity data.

6. The data verifying method according to claim 1 , further comprising: providing a third encoder out of the chip; encoding, through the third encoder, the at least one current updating data to generate the at least one second parity data.

7. The data verifying method according to claim 1 , wherein the step of computing the at least one second parity data with the at least one previous updating data comprises: computing the at least one second parity data with the at least one previous updating data based on error correction code, wherein each of the at least one updating indicator is a computed result of the at least one second parity data and the at least one previous updating data.

8. The data verifying method according to claim 1 , wherein before the step of computing the at least one second parity data with the at least one previous updating data, the data verifying method further comprises: receiving a second combined data, wherein the second combined data comprises a plurality of the second parity data, and a length of the second combined data is not longer than a length of one of the at least one current updating data.

9. A chip, comprising: an input/output (I/O) interface; at least one processing circuit, coupled to the I/O interface; and an encoder, coupled to the at least one processing circuit and the I/O interface, wherein the encoder encodes at least one transmitting data of a to-be-test circuit of the at least one processing circuit to generate at least one first parity data, the at least one transmitting data is a computing result generated by the to-be-test circuit, and the encoder transmits the at least one first parity data without the at least one transmitting data through the I/O interface, wherein the at least one first parity data is used for data verification of the at least one transmitting data; and a decoder, coupled to the at least one processing circuit and the I/O interface, wherein the decoder computes at least one second parity data with at least one previous updating data to generate at least one updating indicator, and the decoder updates the at least one previous updating data at corresponding position recorded in the at least one updating indicator, to generate at least one current updating data, wherein the at least one previous updating data and the at least one current updating data are used for generating the at least one transmitting data.

10. The chip according to claim 9 , wherein the encoder encodes the at least one transmitting data based on error detection code or error correction code, and each of the at least one first parity data is an encoded result of the at least one transmitting data.

11. The chip according to claim 9 , wherein the encoder combines a plurality of the first parity data to form a first combined data, wherein a length of the first combined data is not longer than a length of one of the at least one transmitting data, and the encoder transmits the first combined data through the I/O interface.

12. The chip according to claim 9 , wherein the to-be-test circuit receives at least one updating data and processes the at least one updating data to generate the at least one transmitting data.

13. The chip according to claim 9 , wherein the decoder computes the at least one second parity data with the at least one previous updating data based on error correction code, wherein each of the at least one updating indicator is a computed result of the at least one second parity data and the at least one previous updating data.

14. The chip according to claim 9 , comprising: a plurality of the processing circuits coupled with network topology, wherein merely the at least one transmitting data from one of the processing circuits is allowed to be transmitted via the network topology at a time.

15. A verifying apparatus, comprising: an input/output (I/O) interface, adapted for connecting with a chip; a first encoder; a verifying processor, coupled to the first encoder and the I/O interface, wherein the verifying processor receives at least one first parity data through the I/O interface, the first encoder encodes at least one expected data to generate at least one second parity data, and the verifying processor verifies consistency between one of the at least one first parity data and corresponding second parity data; and a second encoder, coupled to the verifying processor and the I/O interface, wherein the second encoder encodes at least one current updating data to generate at least one third parity data, and the second encoder transmits the at least one third parity data through the I/O interface, wherein the at least one third parity data is related to at least one position where at least one current updating data is different from corresponding previous updating data.

16. The verifying apparatus according to claim 15 , wherein the verifying processor transmits at least one updating data through the I/O interface, and one of the at least one expected data is a computing result of corresponding updating data.

17. The verifying apparatus according to claim 15 , wherein the second encoder combines a plurality of the third parity data to form a combined data, and the second encoder transmits the combined data through the I/O interface, wherein a length of the combined data is not longer than a length of one of the at least one current updating data.