A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure comprising: a porous semiconductor segment adjacent to a first region of a substrate; at least one crystalline epitaxial layer situated over said porous semiconductor segment and over said first region of said substrate; a first semiconductor device situated in said at least one crystalline epitaxial layer over said porous semiconductor segment; a second semiconductor device situated in said at least one crystalline epitaxial layer over said first region of said substrate but not over said porous semiconductor segment; said first region of said substrate having a first dielectric constant, and said porous semiconductor segment having a second dielectric constant that is substantially less than said first dielectric constant such that said porous semiconductor segment reduces signal leakage from said first semiconductor device.
2. The semiconductor structure of claim 1 , wherein a second region of said substrate is situated under said porous semiconductor segment and under said first region of said substrate.
3. The semiconductor structure of claim 1 , further comprising: an electrical isolation region separating said first and second semiconductor devices.
4. The semiconductor structure of claim 3 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.
5. The semiconductor structure of claim 1 , wherein said first semiconductor device is a transistor utilized in a radio frequency (RF) switch.
6. The semiconductor structure of claim 5 , wherein a depth of a source/drain junction of said transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous semiconductor segment.
7. The semiconductor structure of claim 5 , wherein a depth of a source/drain junction of said transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous semiconductor segment.
8. A semiconductor structure comprising: a porous silicon segment adjacent to a first region of a bulk silicon substrate; at least one crystalline epitaxial layer situated over said porous silicon segment and over said first region of said bulk silicon substrate; a first transistor situated in said at least one crystalline epitaxial layer over said porous silicon segment; a second transistor situated in said at least one crystalline epitaxial layer over said first region of said bulk silicon substrate but not over said porous silicon segment; an electrical isolation region separating said first and second transistors.
9. The semiconductor structure of claim 8 , wherein a second region of said bulk silicon substrate is situated under said porous silicon segment and under said first region of said bulk silicon substrate.
10. The semiconductor structure of claim 8 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.
11. The semiconductor structure of claim 8 , wherein said first transistor is utilized in a radio frequency (RF) switch.
12. The semiconductor structure of claim 8 , wherein a depth of a source/drain junction of said first transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous silicon segment.
13. The semiconductor structure of claim 8 , wherein a depth of a source/drain junction of said first transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous silicon segment.
14. A semiconductor structure comprising: a porous silicon segment adjacent to a bulk silicon substrate; at least one crystalline epitaxial layer having a first region situated over said porous silicon segment; said at least one crystalline epitaxial layer having a second region situated over said bulk silicon substrate but not over said porous silicon segment; an electrical isolation region separating said first region of said at least one crystalline epitaxial layer from said second region of said at least one crystalline epitaxial layer.
15. The semiconductor structure of claim 14 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.
16. The semiconductor structure of claim 14 , wherein a first semiconductor device is situated in said first region of said at least one crystalline epitaxial layer and a second semiconductor device is situated in said second region of said at least one crystalline epitaxial layer.
17. The semiconductor structure of claim 16 , wherein said first semiconductor device is a first transistor and wherein a depth of a source/drain junction of said first transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous silicon segment.
18. The semiconductor structure of claim 16 , wherein said first semiconductor device is a first transistor and wherein a depth of a source/drain junction of said first transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous silicon segment.
19. The semiconductor structure of claim 16 , wherein said first semiconductor device is a first transistor that is utilized in a radio frequency (RF) switch.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 10, 2019
December 7, 2021
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